BiCAM-based automated scoring system for digital logic circuit diagrams

1 Introduction

The digital logic design course, which is a basic course in disciplines such as electrical, electronics, and computer engineering, is an important tool in the design of digital system. Traditionally, circuit design teaching is divided into combinational and sequential circuitry. However, this study focuses only on digital system designs built in a combinational circuit structure at the gate level. Logic diagrams constructed with symbolic representations of basic logic gates with a function given by Boolean equations or truth table are an important step in the design process. These diagrams are usually drawn using free or pen-and-paper sketches at first and then collaborated with a digital circuit simulator to test the functionality of the designed circuit. Several studies have been proposed to automate the process of exporting the digital-drawn circuit sketch to a software-based environment to verify for correctness in functionality and in timing [1,2,3,4,5]. The styles used in the drawing of logic gates may vary from one person to another. Correctly interpreting different styles of drawings for a circuit is a tedious task. In recent years, machine learning and image processing algorithms have been used to identify components in free sketch to solve these issues [6,7,8,9,10]. These developments have contributed to the reliability in the identification of components in digital system designs built by the free sketch method. This has led to the possibility of machine-based evaluation of student works in digital logic design course. There has been a serious increase in the transfer of materials used in education to the Internet environment, especially with the COVID-19 pandemic. In addition, this tool will contribute to the evaluation of student-based studies in an environment where online education has become widespread with the COVID-19 pandemic. However, there is a problem here: as the number of students increases, student projects will need to be scored automatically. Because simulating the functionality of each design uploaded to the system is required for grading, such simulation can require many times to complete. This adversely affects the project evaluation period. This is due to the gate-level simulation to verify the logical correctness of the circuit. In this simulation, a table lookup called a netlist is used, which keeps primitive logic gates of the circuit and their connectivity information. The bottleneck of the gate-level simulation performance is due to the poor performance of memory. In other words, read–modify–writeback operation will be done in memory for each logic gate in the circuit. This is essentially a searching problem and again is memory-intensive. This research is motivated by the desire to replace the RAM with content-addressable memory (CAM) to overcome the performance bottleneck in the search process in the lookup table.

Nowadays, the rapid advancement of technology makes us in need of faster computing systems with higher efficiency. The use of CAM, which is also known as associative memory, can provide these features [11]. Unlike conventional memories, CAM uses its parallelism property to search for a part of or an entire stored data (content) within the memory unit in a single clock (CLK) cycle. Random-access memory (RAM) is an example of conventional memories, which requires knowing the location address of the stored data first to extract it. Therefore, it needs multiple CLK cycles to find the desired content, which makes it time-consuming as compared to the CAM [12].

Since the parallelism in CAMs enhances the search process, CAMs simultaneously search all memory cells for the desired content using a key in a single CLK cycle and return the matched contents by a parallel active circuit [13]. The utilization of parallel active circuitry causes an increase in power dissipation and hardware cost. To overcome this, different energy-saving designs and technologies for CAMs are proposed in the literature. Eshraghian et al. [14] proposed a new approach of modeling CAM by using memory resistor (memristor)-based CAM where the non-volatile characteristic and the nanoscale geometry of using a combination of memristor MOS devices to help to increase the packing density. Abdelhadi and Lemieux [15] proposed a technique for building up binary content-addressable memory (BiCAM) by using the standard SRAM blocks in field-programmable gate arrays (FPGAs). Also, they used the hierarchical search method to achieve higher storage efficiency. Kim and Kim [16] have presented a small-area and low-power static architecture BiCAM based on Nano-Electromechanical Memory Switch for nonvolatile data storage. Satyanarayana and Sridevi [17] proposed a pre-charge controller-based ternary content-addressable memory (TCAM) architecture. Where the pre-charge controller predicts the mismatched lines in the pre-charge phase, their design exhibits a 16.6% reduction in power. Riaz et al. [18] proposed a cell design of the TCAM in order to reduce power consumption. They reviewed the architectural level and optimized solution of their design, which can be used as BiCAM or TCAM.

Despite all these drawbacks, CAMs have a well-suited throughput and response time for data-intensive and time-sensitive applications. They are considered as a good trade-off and popular for many applications such as packet forwarding and packet classification in network routers, data compression, artificial neural networks, network security, and pattern recognition and matching [19,20].

The existing CAMs are divided into two types: BiCAM, where each unit cell of the memory can have either “0” or “1” states and TCAM that has the same cell states as the BiCAM with an additional “don’t care” (“X”) state [21]. Based on the implementation technique, CAMs are categorized as application-specific integrated circuit (ASIC)-based (conventional) and FPGA-based [22]. Contrary to ASIC, an FPGA device is a useful platform for digital system designers because of its super-flexibility and reconfigurability. However, most FPGA architectures do not have a CAM block unit. Multiple methods are presented for the FPGA-based CAM design. These methods include block RAM (BRAM)-based CAMs [23], distributed RAM-based CAMs [24], and flip-flop-based CAMs [25].

In this article, it is focused on the problem of searching the netlist memory map generated for the digital circuit to verify the functional description for digital circuits. This research tries to demonstrate the features of using CAMs instead of conventional memories by providing a comparison between an FPGA-based digital circuit examiner by using two different approaches, BiCAM and RAM, and discuss their results in terms of resource usage and latency. The data samples can be obtained by reading a handwritten logic circuit design by using the machine learning technique [10], mathematical morphology operations [26], and Fourier descriptors [27], where the used inputs, outputs, and the used components are scanned and listed. The remainder of this article is structured as follows: In Section 2, the structure of the conventional BiCAM is explained. Section 3 discusses how the BiCAM-based netlist table architecture is implemented, while Section 5 details the proposed work. In Section 5, the performance results of logic circuit evaluation by using both CAM and RAM approaches are explained. In Section 6, the entire work of this study is concluded.

2 BiCAM organization

Generally, a BiCAM is organized in such a way:

• Argument register: it consists of n-bits of the desired word (content) to be searched for.

• Key register: it consists of n-bits and specifies, which bits part of the argument register needs to be compared with words in memory. If all bits within register are set to 1, the entire word should be compared. Otherwise, only the bits that set to 1 will be compared.

• Associative memory array: it consists of the words (content nxm bits) that are going to be compared with the argument register.

• Match register: it consists of m-bits, each bit is corresponded to one word in the memory array, and if the match happens, the corresponding bit is set to 1.

To understand how BiCAM works, a simple CAM model is given in Figure 1. Where it is clear that the CAM consists of 5 words (rows) and each word has 4 bits (CAM cell), so in total it is 20 CAM cells. Each cell of the CAM has two tasks: data storage and comparison. For each word, there is a matching line attached to the match register. There is also a search line for each cell attached to the corresponding bit of the key register. The search process in CAMs begins by loading the value of the required search data into the argument register; then, the value gets masked with the key register to have only the desired bits remaining. The comparison process occurs for each CAM cell by comparing its stored bits against the bits in their corresponding search lines. The match lines will have the value of the comparison results where it shows if the match condition occurred or not. The circuit that will do the matching for a word in the CAM is given in Figure 2.

Figure 1

Example search operation in a CAM with 5 words having 4 bits.

Figure 2

Matching logic for each word (n-bits) in CAM.

3 BiCAM-based netlist table architecture

The BiCAM memory design proposed in this study was implemented on Altera’s EP2C70F896C6 FPGA board. The design contains bit cells, comparison unit, ROM (read only memory), and encoder modules. The inputs of proposed design are as follows: CLK, write or read enable (W_R), reset, 8-bit address pin, 15-bit argument register, 15-bit key register, 8-bit match register, and 15-bit data input. Each bit cell of the BiCAM has consisted of two main components: The first one is flip-flops on which the data can be stored or retrieved and the second one is a comparison circuit to check whether there is a match that occurs between the stored value within the flip-flops and the search value that will come from the argument register. Each bit cell of the BiCAM is provided with a comparison circuit that is connected to its corresponding flip-flop’s output and search value as input where a logically comparing operation is realized. The output of this comparison circuit is connected to the match flag register. In Figure 3, the RTL diagram of the bit cell is given.

Figure 3

RTL diagram of the one-bit cell with comparison circuit in the proposed BiCAM.

The designed Bit_cell (shown in Figure 3) module was duplicated sequentially to form an entire row (string) consisting of 15 columns by using the generate function in the VHDL language. Each row of the BiCAM has its match line that is linked to the outputs of the comparison circuits of each bit cell of the related row. To have the array-shaped design of the proposed BiCAM, the generate function is used again to create a 256 × 15 Bit_cell array (matrix). To initialize the proposed BiCAM with desired initial data, a storage unit should be used to load the initial data into the BiCAM during the initialization process. For the proposed design, a ROM was suggested to be used as the storage unit as it is suitable for the proposed design and only load data into the BiCAM are required. The vendor-specific intellectual property core IP blocks are a useful tool and became a common design methodology when designs are bigger and more complicated. Using Megafunctions instead of writing your code is considered a time-saving method while designing FPGA. Altera provides multiple types of memories in Megafunctions such as ALTSYNCRAM, ALTDPRAM, ALT3PRAM, and LPM_RAM_DQ Megafunctions.

The 1-port lpm_ROM Megafunction is chosen for the proposed design, where it is fully parameterizable and allows both synchronous and asynchronous single ports. The lpm_ROM needed to be initialized with desired initial data while configuring. A memory initialization file (.mif) or hexadecimal (.hex) file should be used with the same name as the lpm_ROM in the project directory. Each row of the proposed BiCAM represents a single data (word) and is connected to its match_line, which is already connected to the 256-bit match_flag register. The last part of the design presented in this study is an encoder circuit that gives the address of the data in the CAM. The inputs of this circuit are the outputs of the register consisting of match flags that indicate whether the searched data are found in each line of the CAM. Since the CAM consists of 256 rows in our design, the encoder circuit used is in 256 × 8 format.

4 Proposed work

In this study, netlist files obtained by machine learning-based or another methods were used for the recognition of hand-drawn digital circuits. The accuracy level of the outputs produced for a specified set of inputs for the logic circuit functions in this file has been determined by the FPGA-based BiCAM memory approach. The proposed work is divided into two task blocks: mapping circuit and logic engine as shown in Figure 4.

Figure 4

Overview of the proposed architecture.

The mapping phase generates the configuration memory for input circuit design according to the netlist file. In other words, the memory image of the circuit is obtained. In this study, it is assumed that digital circuits consist of primitive gates with two inputs. The first and second columns in BiCAM store the input variables that correspond to a particular gate. The third column stores the output variable of each gate. The last column stores the type information of the Boolean primitive in the logic circuit. A three-bit encoding scheme is required to represent all logic gates. Table 1 shows the encoded notation used to express the different gate types in the study.

A 4-bit space is reserved for each input and output variables in the circuit. A maximum of 16 variables can be encoded with this 4-bit notation. This format used in the study has no basis and is given only for illustration. Depending on the size of the circuit, the bit space in the notation can be increased or decreased. The encoding of the variables is determined according to their order in the netlist file. For example, if the first line in the file is “and: g1 in: x y out n1,” the input x here will be encoded as 0001, and the variable y will be encoded as 0010, and if the output variable is n1, it will be encoded as 0011. The empty variables in the netlist file will be represented as “0000.” This situation is summarized in Table 2.

Based on this information, Table 3 illustrates the memory map of logic circuit based on the netlist file shown in Figure 4. The algorithm shown in Figure 5 can be divided into three phases. These are evaluating, updating, and scheduling.

Figure 5

Algorithm to determine the logic behavior of a circuit.

The evaluation phase starts with the step of searching the netlist of each minterm in the answer key file and transferring their input signals to the relevant variables. Then, the output of Boolean primitive is evaluated according to these input signals. If a change occurs in the output signal of a gate, the logic engine first updates the output and records it as an event for later evaluation. These events are thrown into the running queue according to the FIFO structure. After evaluating and updating the netlist file according to the relevant minterm in the answer key, all events in the queue are executed one by one.

To prove the algorithm, a small circuit is made to test various types of Boolean primitives. The following steps show the operation of algorithm on the circuit, a full adder with only the output of sum. One of the XOR gates was intentionally opened to AND, OR, and NOT gates so as not to expand the schematic design of the design.

Step 1: The netlist and answer key files creating for the example circuit.

Step 2: Retrieving the minterm expression (product term) from answer key file and evaluating in all related words of the netlist memory map.

Step 3: Evaluating each event in the event queue according to the FIFO rule as in Step 2 and continuing the process until the queue is empty.

Step 4: Updating the evaluation score: Since S = 1 in the netlist file, the evaluation score is updated (score++) and go to Step 1.

The aforementioned steps are repeated for the other three input vectors in the answer key file, and the evaluation score is obtained. If the score found is equal to the number of input vectors in the answer key, it indicates that the logic circuit is working perfectly. Otherwise, it is concluded that the circuit produces wrong results in some input vectors and the schematic design of the circuit should be checked again.

5 Evaluation and experimental results

This section will present how to evaluate all the materials discussed in previous sections for the use of CAM in evaluating digital logic circuits for logical accuracy. A simple test circuit is presented in Section 4 to demonstrate how the proposed design meets expectations. The performance of the design is demonstrated by comparing the traditional RAM and CAM structures of the netlist file required to compute the output of a gate with a given input vector. The problem of the search task for the computation takes up a major portion of the evaluation time of the digital circuits. In this section, three different architectures will be examined and discussed to compare the performance in the search task also by the logic simulation software [28]. These are linear scanning, parallel linear scanning, and parallel linear scanning with binary tree.

In the linear searching, the logic evaluation block may perform a search operation, continuously searching for a gate suitable according to the given input vector in memory. This search requires O( x ) time in a memory with elements. In order to speed up the search process and save time, the linear memory space should be subdivided for concurrently search. For example, if the memory space with x elements is divided into m subpartitions with n elements, the time complexity of the search process will be O( n ) + O( m ). Here, O( n ) denotes the search time in each subdivision, while O( m ) denotes the search time between the results obtained from these subdivisions. If the results from the subdivisions are organized with a binary tree structure architecture, the time complexity will be O( m ). Table 4 summarizes the architectures presented in this section to demonstrate the effectiveness of the design.

When the table is examined, the search algorithms have different times of complexity depending on the size of the m and n numbers; in case, they use RAM-type memory. The fastest algorithm in this table is PLS with binary tree, but as the number of roots in the binary tree structure increases, the resource usage may reach the maximum level or even not be enough. If m = n , it is the PLS algorithm with optimal performance (O( m )) among the search algorithms in this table. Considering that the performance of the software-based search algorithm is O( x ), the search speed will increase n times ( O ( x ) O ( m ) = O ( x ) / O ( x n ) ≈ n ). In the CAM-based memory usage proposed in this study, the time complexity will be O(1) in all algorithms.

6 Conclusion

The inclusion of image processing, machine learning, and other technologies in the education process contributes to the evaluation process of the courses. The schematic design of digital circuits is of great importance in the digital design course, which is one of the basic courses of departments such as electrical, electronics, and computer engineering. In this course, students are given homework and projects to increase their experience. The evaluation process of these designs is a laborious task and takes time. Along with human–computer interaction, the schematic design of digital circuit can be diagnosed with machine learning methods in recent years. In this study, we placed the netlist file of a circuit obtained by machine learning into a CAM with a time complexity of O(1) instead of a conventional RAM. In this way, the verification process of the circuit obtained by the machine learning method is faster than the other algorithms mentioned in the study. There is a data structure known as a hash table or map in the literature, which is the same as the time complexity of the proposed design. It uses a hash function (key) to create this structure. However, a reasonable choice of “key” calculation algorithm for each datum in the table and strategies such as mass storage maintenance or key recalculation to accommodate collisions are obstacles to this data structure. CAM is a hardware solution to this problem. The comparison circuit in CAM’s architecture uses more resources than conventional RAM. This proposed design will consume more resource usage, but, as a trade-off, will achieve the logic circuit evaluation process faster. The effect of CAM on the time complexity in the search process has led to the emergence of varieties of these memory types in the literature. The implementation of other CAM types in the literature, which are more efficient in terms of resource and power usage instead of memory in the proposed architecture, is considered in future studies.