Abstract
Digital circuits are widely utilized in computers, because they provide models for various digital components and arithmetic operations. Arithmetic circuits are a subclass of digital circuits that are used to execute Boolean algebra. To avoid problems like the infamous Pentium FDIV bug, it is critical to ensure that arithmetic circuits are correct. Formal verification can be used to determine the correctness of a circuit with respect to a certain specification. However, arithmetic circuits, particularly integer multipliers, represent a challenge to current verification methodologies and, in reality, still necessitate a significant amount of manual labor. In my dissertation we examine and develop automated reasoning approaches based on computer algebra, where the word-level specification, modeled as a polynomial, is reduced by a Gröbner basis inferred by the gate-level representation of the circuit. We provide a precise formalization of this reasoning process, which includes soundness and completeness arguments and adds to the mathematical background in this field. On the practical side we present an unique incremental column-wise verification algorithm and preprocessing approaches based on variable elimination that simplify the inferred Gröbner basis. Furthermore, we provide an algebraic proof calculus in this thesis that allows obtaining certificates as a by-product of circuit verification in order to boost confidence in the outcomes of automated reasoning tools. These certificates can be efficiently verified with independent proof checking tools.
Article note
The dissertation of Dr. Daniela Kaufmann has been awarded by the GI Dissertation Award 2020.
A German summary of the dissertation already appeared in Steffen Hölldobler et al. (eds). Ausgezeichnete Informatikdissertationen 2020. Lecture Notes in Informatics, Gesellschaft für Informatik e. V.
About the author
Dr. Daniela Kaufmann received her PhD in Computer Science from Johannes Kepler University Linz under the supervision of Prof. Armin Biere. Her first publication about formal verification of multipliers using computer algebra has been awarded the best paper award at the Intl. Conference of Formal Methods in Computer-Aided Design (FMCAD), one of the top-tier conferences for hardware verification. In 2020 Daniela Kaufmann received the JKU Young Researchers’ Award. Prior to her PhD, Daniela Kaufmann obtained a Bachelor’s degree in Mathematical Engineering and a Master’s degree in Computer Mathematics, both from Johannes Kepler University Linz. Her research interests cover applied formal methods, in particular hardware verification, proof systems as well as satisfiability solving and algebraic reasoning.
References
1. Barrett, C., Fontaine, P. & Tinelli, C. The Satisfiability Modulo Theories Library (SMT-LIB). (www.SMT-LIB.org, 2016).Search in Google Scholar
2. Biere, A. Collection of Combinational Arithmetic Miters Submitted to the SAT Competition 2016. SAT Competition 2016. B-2016-1 pp. 65–66 (2016).Search in Google Scholar
3. Buchberger, B. Ein Algorithmus zum Auffinden der Basiselemente des Restklassenringes nach einem nulldimensionalen Polynomideal. (University of Innsbruck, 1965).Search in Google Scholar
4. Beame, P., and Liew, V. Towards Verifying Nonlinear Integer Arithmetic. CAV 2017. 10427 pp. 238–258 (2017).10.1007/978-3-319-63390-9_13Search in Google Scholar
5. Bryant, R. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Trans. Comput. 35, 677–691 (1986).10.1109/TC.1986.1676819Search in Google Scholar
6. Chen, Y., and Bryant, R. Verification of Arithmetic Circuits with Binary Moment Diagrams. DAC 1995. pp. 535–541 (1995).Search in Google Scholar
7. Ciesielski, M., Su, T., Yasin, A., and Yu, C. Understanding Algebraic Rewriting for Arithmetic Circuit Verification: a Bit-Flow Model. IEEE TCAD. 39, 1346–1357 (2020).10.1109/TCAD.2019.2912944Search in Google Scholar
8. Clegg, M., Edmonds, J. & Impagliazzo, R. Using the Groebner Basis Algorithm to Find Proofs of Unsatisfiability. Symposium On Theory Of Computing, STOC 1996. pp. 174–183 (1996).10.1145/237814.237860Search in Google Scholar
9. Cox, D., Little, J. & O’Shea, D. Ideals, Varieties, and Algorithms. Springer-Verlag New York (1997).10.1007/978-1-4757-2693-0Search in Google Scholar
10. Heule, M. & Biere, A. Proofs for Satisfiability Problems. All About Proofs, Proofs For All Workshop, APPA 2014. 55 pp. 1–22 (2015).Search in Google Scholar
11. Hunt, W., Kaufmann, M., Strother Moore, J., and Slobodova, A. Industrial Hardware and Software Verification with ACL2. Philos. Trans. Royal Soc. A. 375, 20150399 (2017).10.1098/rsta.2015.0399Search in Google Scholar PubMed PubMed Central
12. Kaufmann, D. Formal Verification of Multiplier Circuits using Computer Algebra. (Informatik, Johannes Kepler University Linz, 2020).Search in Google Scholar
13. Kaufmann, D. & Biere, A. AMulet 2.0 for Verifying Multiplier Circuits. TACAS (2). 12652 pp. 357–364 (2021), https://github.com/d-kfmnn/amulet2.Search in Google Scholar
14. Kaufmann, D., Biere, A., and Kauers, M. Verifying Large Multipliers by Combining SAT and Computer Algebra. FMCAD 2019. pp. 28–36 (2019).10.23919/FMCAD.2019.8894250Search in Google Scholar
15. Kaufmann, D., Biere, A., and Kauers, M. From DRUP to PAC and Back. DATE 2020. pp. 654–657 (2020).10.23919/DATE48585.2020.9116276Search in Google Scholar
16. Kaufmann, D., Biere, A., and Kauers, M. Incremental Column-wise Verification of Arithmetic Circuits using Computer Algebra. FMSD. 56, 22–54 (2020).10.1007/s10703-018-00329-2Search in Google Scholar PubMed PubMed Central
17. Kaufmann, D., Biere, A. & Kauers, M. SAT, Computer Algebra, Multipliers. Vampire 2018 And Vampire 2019. The 5th And 6th Vampire Workshops. 71 pp. 1–18 (2020), https://github.com/d-kfmnn/amulet.Search in Google Scholar
18. Kaufmann, D., Fleury, M., and Biere, A. Pacheck and Pastèque, Checking Practical Algebraic Calculus Proofs. FMCAD 2020. pp. 264–269 (2020), http://fmv.jku.at/pacheck_pasteque/.Search in Google Scholar
19. Kuehlmann, A., Paruthi, V., Krohm, F. & Ganai, M. Robust Boolean reasoning for equivalence checking and functional property verification. IEEE TCAD. 21, 1377–1394 (2002).10.1109/TCAD.2002.804386Search in Google Scholar
20. Mahzoon, A., Große, D., and Drechsler, R. RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC 2019. pp. 185:1–185:6 (2019), http://sca-verification.org/.10.1145/3316781.3317898Search in Google Scholar
21. Mayr, E. Membership in polynomial ideals over Q is exponential space complete. STACS 89. pp. 400–406 (1989).10.1007/BFb0029002Search in Google Scholar
22. Parhami, B. Computer Arithmetic – Algorithms and Hardware designs. (Oxford University Press, 2000).Search in Google Scholar
23. Pavlenko, E., Wedler, M., Stoffel, D., Kunz, W., Wienand, O. & Karibaev, E. Modeling of Custom-Designed Arithmetic Components for ABL Normalization. Forum On Specification And Design Languages, FDL 2008. pp. 124–129 (2008).10.1109/FDL.2008.4641433Search in Google Scholar
24. Ritirc, D., Biere, A., and Kauers, M. Column-Wise Verification of Multipliers Using Computer Algebra. FMCAD 2017. pp. 23–30 (2017).10.23919/FMCAD.2017.8102237Search in Google Scholar
25. Ritirc, D., Biere, A., and Kauers, Manuel. A Practical Polynomial Calculus for Arithmetic Circuit Verification. SC2 Workshop 2018. pp. 61–76 (2018).Search in Google Scholar
26. Sayed-Ahmed, A., Große, D., Kühne, U., Soeken, M., and Drechsler, R. Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction. DATE 2016. pp. 1048–1053 (2016).10.3850/9783981537079_0248Search in Google Scholar
27. Sharangpani, H., and Barton, M. Statistical Analysis of Floating Point Flaw in the Pentium Processor. (1994).Search in Google Scholar
28. Stoffel, D., and Kunz, W. Equivalence Checking of Arithmetic Circuits on the Arithmetic Bit Level. IEEE TCAD. 23, 586–597 (2004).10.1109/TCAD.2004.826548Search in Google Scholar
29. Vasudevan, S., Viswanath, V., Sumners, R., and Abraham, J. Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Comput. 56, 1401–1414 (2007).10.1109/TC.2007.1073Search in Google Scholar
30. Yu, C., Brown, W., Liu, D., Rossi, A., and Ciesielski, M. Formal Verification of Arithmetic Circuits by Function Extraction. IEEE TCAD. 35, 2131–2142 (2016).10.1109/TCAD.2016.2547898Search in Google Scholar
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