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BY-NC-ND 3.0 license Open Access Published by De Gruyter Open Access March 28, 2012

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

  • Mohammad Khan EMAIL logo and Abdul Ansari
From the journal Open Computer Science


The Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3, 13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, and dTDMA in SoC. The TDMA systems use a fixed number of timeslots. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [14]. In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. We have obtained the maximum clock frequency of 2.09 GHz for 96(4 × 8 × 3) IP cores connected in a mesh topology. The presented architecture demonstrates their superior functionality in terms of speed, latency, area, and power consumption as compared with the existing implementation [14]. The maximum power consumption of the proposed area-efficient programmable arbiter is 0.625 mW. The design is synthesized using 180nm TSMC Technology.

[1] ARM, Multi-layer AHB, Overview, 2010 Search in Google Scholar

[2] Bell Jr. R.H., Kang Ch.Y., John L., Swartzlander Jr. E.E., CDMA as a multiprocessor interconnect strategy, In: Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on, 2, 1246–1250, 2001 10.1109/ACSSC.2001.987690Search in Google Scholar

[3] Chita R.D., Nicopoulos Ch., Narayanan V., Network-on-chip architectures: a holistic design exploration, In: Lecture Notes in Electrical Engineering, Springer, 2009 10.1007/978-90-481-3031-3Search in Google Scholar

[4] Das S., Fan A., Chen K.-N., Tan C.S., Checka N., Reif R., Technology, performance, and computer-aided design of three-dimensional integrated circuits, In: Proceedings of the International Symposium on Physical Design, Phoenix, Arizona, USA, 108–115, 2004 10.1145/981066.981091Search in Google Scholar

[5] Eleccion M., The electronic watch, Spectrum, IEEE, 10, 24–32, 1973 in Google Scholar

[6] Feero B.S, Pande P.P., Networks-on-chip in a three-dimensional environment: a performance evaluation, IEEE Trans. Comp., 58, 32–45, 2009 in Google Scholar

[7] Forrer M.P., Survey of circuitry for wristwatches, Proceedings of the IEEE 60, 1047–1054, 1972 in Google Scholar

[8] Joyner J.W., Zarkesh-Ha P., Meindl J.D., A stochastic global net-length distribution for a three-dimensional systemon-a-chip (3D-SoC), In: ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, 147–151, 2001 Search in Google Scholar

[9] Khan M.A., Ansari A.Q., 128-bit high-speed fifo for network-on-chip, In: IEEE International Conference on Emerging Trends in Computing, 116–121, 2011 Search in Google Scholar

[10] Krewell G., Multicore showdown, microprocessor report, Tech. Rep., 19, 41–45, 2005 Search in Google Scholar

[11] Lai B.-C.C., Schaumont P., Verbauwhede I., CT-Bus: a heterogeneous CDMA/TDMA bus for future SoC, In: Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on, 2, 1868–1872, 2004 in Google Scholar

[12] Li F., Nicopoulos C., Richardson T., Xie Y., Narayanan V., Kandemir M., Design and management of 3D chip multiprocessors using network-in-memory, In: Comp. Arch., 2006. ISCA’ 06. 33rd International Symposium on, 130–141, 2006 10.1145/1150019.1136497Search in Google Scholar

[13] Pasricha S., Dutt N., On-Chip Communication Architectures, Morgan Kaufmann Publications, 2008 10.1016/B978-0-12-373892-9.00006-2Search in Google Scholar

[14] Richardson T.D., Nicopoulos C., Park D., Narayanan V., Xie Y., Das C., Degalahal V., A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks, In: VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design, 19th International Conference on Jan. 8, 2006 10.1109/VLSID.2006.10Search in Google Scholar

Published Online: 2012-3-28
Published in Print: 2012-3-1

© 2012 Versita Warsaw

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

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