S. Karasahin, M. Dammasch
August 25, 2016
The technological progress of microelectronic devices is directly coupled with the ability to produce transistor circuits and interconnects on the wafer level with increasingly small dimensions while providing equal or even better electrical properties and functionality. Therefore every new generation of microchip manufacturing is a challenge for the existing production technologies to compete with the raised requirements as well as for the material scientific methods to characterize and control the properties of the incorporated dielectrics and deposited metal layers with dimensions in the nm range. The following article will illustrate the investigation methods that have been applied for the development of electrolessly plated copper layers of less than 3 nm thickness to provide a conductive copper seed for subsequent copper electroplating to fill Dual Damascene interconnects of the 14 nm or 10 nm technology node. The methods used are AFM, Ellipsometry, 4-point resistivity, XPS, EELS, XRF, XRD, FIB/HR-STEM, HR-TEM.