A conventional analog to digital converter (ADC) faces many issues with leading-edge technologies due to noise, manufacturing deviations, signal swings, etc. Thus, we pursue to design an adaptive spiking neural ADC (SN-ADC) with promising features, e.g., robust to noise, low-power, technology scaling issues, and low-voltage operation. Therefore, our approach promises to be technology agnostic, i.e., effectively translatable to aggressive new technologies. It supports machine learning and self-x (self-calibration, self-healing) that needs for industry 4.0 and the internet of things (IoTs). In this work, we design an adaptive spike-to-rank coding (ASRC), which is the main part of the spiking neural ADC. The ASRC is based on CMOS memristors emulating short-term plasticity (STP) and long-term plasticity (LTP) biological synapses. The proposed ASRC compensates deviations by adapting the weights of the synapses. Also, ASRC is designed using XFAB 0.35 μm CMOS technology and Cadence design tools. In addition, ASRC is simulated to test its performance in the temperature range (−40°C to 85°C).