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Advanced Optical Technologies

Editor-in-Chief: Pfeffer, Michael

CiteScore 2018: 1.42

SCImago Journal Rank (SJR) 2018: 0.499
Source Normalized Impact per Paper (SNIP) 2018: 1.346

In co-publication with THOSS Media GmbH

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Volume 6, Issue 3-4


Patterning roadmap: 2017 prospects

Mark Neisser
  • Corresponding author
  • Kempur Microelectronics, Inc., No. 4 Zhuyuan Street, Tianzhu Free Trade Zone, Beijing 101312, China
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Published Online: 2017-06-08 | DOI: https://doi.org/10.1515/aot-2017-0039


Road mapping of semiconductor chips has been underway for over 20 years, first with the International Technology Roadmap for Semiconductors (ITRS) roadmap and now with the International Roadmap for Devices and Systems (IRDS) roadmap. The original roadmap was mostly driven bottom up and was developed to ensure that the large numbers of semiconductor producers and suppliers had good information to base their research and development on. The current roadmap is generated more top-down, where the customers of semiconductor chips anticipate what will be needed in the future and the roadmap projects what will be needed to fulfill that demand. The More Moore section of the roadmap projects that advanced logic will drive higher-resolution patterning, rather than memory chips. Potential solutions for patterning future logic nodes can be derived as extensions of ‘next-generation’ patterning technologies currently under development. Advanced patterning has made great progress, and two ‘next-generation’ patterning technologies, EUV and nanoimprint lithography, have potential to be in production as early as 2018. The potential adoption of two different next-generation patterning technologies suggests that patterning technology is becoming more specialized. This is good for the industry in that it lowers overall costs, but may lead to slower progress in extending any one patterning technology in the future.

Keywords: EUV; IRDS; ITRS; nanoprint technology; roadmap

About the article

Mark Neisser

Mark Neisser is the Technology Director at Kempur Microelectronics Inc, where he directs the development of photoresist and other new products. Previously, he worked at SEMATECH in the Lithography Program where he led a team that did research into expanding current EUV resist material platforms and to enable new solutions such as metal-based EUV resist. He earned his Bachelor’s degree at Cornell University and his Master’s and PhD degrees at the University of Michigan, Ann Arbor, all in Chemistry. Dr Neisser worked at IBM for 16 years where he focused on packaging materials and semiconductor lithography research, followed by positions managing research and development of photoresists and of ancillary materials for lithography at Arch and AZ electronic materials, respectively. He is the author of over three dozen patents and 100 technical publications and is the inventor of double exposure as a resolution enhancement for lithography. Dr Neisser was the chairman of the ITRS lithography technical working group starting in 2012 and is the current chair of the International Roadmap for Devices and Systems (IRDS) Lithography Technical Working Group.

Received: 2017-05-15

Accepted: 2017-05-15

Published Online: 2017-06-08

Published in Print: 2017-06-27

Citation Information: Advanced Optical Technologies, Volume 6, Issue 3-4, Pages 143–148, ISSN (Online) 2192-8584, ISSN (Print) 2192-8576, DOI: https://doi.org/10.1515/aot-2017-0039.

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