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A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure

Doru Chiper
  • Department of Applied Electronics, Technical University “Gh. Asachi” Iasi, B-dul Carol I, No.11, RO-6600, Iasi, Romania
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Published Online: 2011-06-28 | DOI: https://doi.org/10.2478/s13537-011-0015-z

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Abstract

A new VLSI algorithm and its associated systolic array architecture for a prime length type IV discrete cosine transform is presented. They represent the basis of an efficient design approach for deriving a linear systolic array architecture for type IV DCT. The proposed algorithm uses a regular computational structure called pseudoband correlation structure that is appropriate for a VLSI implementation. The proposed algorithm is then mapped onto a linear systolic array with a small number of I/O channels and low I/O bandwidth. The proposed architecture can be unified with that obtained for type IV DST due to a similar kernel. A highly efficient VLSI chip can be thus obtained with good performance in the architectural topology, computing parallelism, processing speed, hardware complexity and I/O costs similar to those obtained for circular correlation and cyclic convolution computational structures.

Keywords: parallel algorithm; parallel architecture; systolic arrays

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About the article

Published Online: 2011-06-28

Published in Print: 2011-06-01

Citation Information: Open Computer Science, Volume 1, Issue 2, Pages 243–250, ISSN (Online) 2299-1093, DOI: https://doi.org/10.2478/s13537-011-0015-z.

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© 2011 Versita Warsaw. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License. BY-NC-ND 3.0

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