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PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

K. Rahimunnisa / P. Karthigaikumar
  • Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, 641 032, India
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/ N. Christy / S. Kumar / J. Jayakumar
Published Online: 2013-12-28 | DOI: https://doi.org/10.2478/s13537-013-0112-2


As the technology is growing day by day, information security plays a very important role in our lives. In order to protect the information, several cryptographic algorithms have been proposed. The aim of this paper is to present an effective Advanced Encryption Standard (AES) architecture to achieve high throughput for security applications. The Parallel Sub-Pipelined architecture (PSP) is proposed in order to obtain high throughput. The proposed architecture is also compared with loop unrolled, pipelined, sub-pipelined, parallel and parallel pipelined architecture in terms of throughput. The AES algorithm using Parallel Sub-Pipelined architecture was prototyped in FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit).The proposed architecture yielded a throughput of 59.59 Gbps at a frequency of 450.045 MHz on FPGA Virtex XC6VLX75T which is higher than the throughput yielded in other architectures. In ASIC 0.13 µm technology, the proposed architecture yielded a throughput of 25.60 Gbps and in 0.18 µm, it yielded a throughput of 20.56 Gbps.

Keywords: cryptography; AES; FPGA; ASIC; parallel sub-pipelined; throughput

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About the article

Published Online: 2013-12-28

Published in Print: 2013-12-01

Citation Information: Open Computer Science, Volume 3, Issue 4, Pages 173–186, ISSN (Online) 2299-1093, DOI: https://doi.org/10.2478/s13537-013-0112-2.

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© 2013 Versita Warsaw. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License. BY-NC-ND 3.0

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