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Open Engineering

formerly Central European Journal of Engineering

Editor-in-Chief: Noor, Ahmed

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A power efficient bandwidth regulation technique for a low-noise high-gain RF wideband amplifier

1Department of Electrical and Electronic Engineering, Bangladesh Univ. of Engineering and Technology (BUET), Dhaka, 1000, Bangladesh

© 2012 Versita Warsaw. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License. (CC BY-NC-ND 3.0)

Citation Information: Open Engineering. Volume 2, Issue 3, Pages 383–391, ISSN (Online) 2391-5439, DOI: https://doi.org/10.2478/s13531-012-0009-1, July 2012

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Published Online:


In this paper, a single-stage deep sub-micron wideband amplifier (LNA) using a reactive resonance tank and passive port-matching techniques is demonstrated operating in the microwave frequency range (K band). A novel power-efficient bandwidth (BW) regulation technique is proposed by incorporating a small impedance in the resonance tank of the amplifier configuration. It manifests a forward gain in the range of 5.9–10.7 dB covering a message bandwidth of 10.6–6.3 GHz. With regulation, input-output reflection parameters (S 11, S 22) and noise figure can be manipulated by −12.7 dB, −22.7 dB and 0.36 dB, respectively. Symmetric regulation is achieved for bandwidth and small signal gain with respect to moderate tank impedance (36.5% and −26.8%, respectively) but the effect on noise contribution remains relatively low (increase of 7% from a base value of 2.39 dB). The regulated architecture, when analyzed with 90 nm silicon CMOS process, supports low power (9.1 mW) on-chip communication. The circuit is tested with a number of combinations for tank (drain) impedance to verify the efficiency of the proposed technique and achieves better figures of merit when compared with published literature.

Keywords: Bandwidth regulation; Wideband amplifier; High gain; 90 nm

  • [1] Saraswat K.C., Mohammadi F., Effect of interconnection scaling on time delay of VLSI circuits, IEEE TED, 1982, 29, 645–650 http://dx.doi.org/10.1109/T-ED.1982.20757 [Crossref]

  • [2] Sun M., Zhang Y.P., Zheng G.X., Yin W.Y., Performance of Intra-Chip Wireless Interconnect Using On-Chip Antennas and UWB Radios, IEEE TAP, 2009, 57, 2756–2762

  • [3] Lager I.E., De Hoop A.T., Inter-chip and intra-chip pulsed signal transfer between transmitting and receiving loops in wireless interconnect configurations, In: Proceedings of European Microwave Conf. (Sept. 28–30, 2010 Paris France), 2010, 577–580

  • [4] Chang M.F., Roychowdhury V.P., Zhang L., Shin H., Qian Y., RF/wireless interconnect for inter- and intra- chip communications, Proceedings of the IEEE, 2001, 89, 456–466 http://dx.doi.org/10.1109/5.920578 [Crossref]

  • [5] Casu M.R., Durisi G., Implementation aspects of a transmitted-reference UWB receiver, Journal of Wireless Communications and Mobile Computing, 2005, 5, 551–566 http://dx.doi.org/10.1002/wcm.309 [Crossref]

  • [6] Malik W.Q., Stevens C.J., Edwards D.J., Multipath Effects in Ultrawideband Rake Reception, IEEE TAP, 2008, 56, 507–514 [Web of Science]

  • [7] Saha P.K., Sasaki N., Kikkawa T., A CMOS Monocycle Pulse Generation Circuit in a Ultra- Wideband Transmitter for Intra/Inter Chip Wireless Interconnection, Japanese Journal of Applied Physics, 2005, 44, 2104–2108 http://dx.doi.org/10.1143/JJAP.44.2104 [Crossref]

  • [8] Chen M., Lin J., A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS, IEEE MWCL, 2009, 19, 323–325

  • [9] Kim J., Hoyos S., Silva-Martinez J., Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback With Simultaneous Noise, Gain, and Bandwidth Optimization, IEEE TMTT, 2010, 58, 2340–2351 [Web of Science]

  • [10] Leung B., VLSI for Wireless Communication, 1st ed., Prentice Hall India, New Delhi, 2002

  • [11] Doan C.H., Emami S., Niknejad A.M., Broadersen R.W., Millimeter-wave CMOS design, IEEE JSSC, 2005, 40, 144–155

  • [12] Wang T.P., Wang H., A Broadband 42–63 GHz Amplifier Using 0.13 μm CMOS Technology, In: Proceedings of IEEE/MTT-S Int. Microwave Symposium (June 3–8, 2007 Honolulu Hawaii), 2007, 1779–1782

  • [13] Masud M.A., Zirath H., Ferndahl M., Vickes H.O., 90 nm CMOS MMIC amplifier, In: Proceedings of IEEE RFIC Symp. (June 6–8, 2004 Fort Worth Texas), 2004, 201–204

  • [14] Rashid S., Ali S., Roy A., Rashid H., A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 μm CMOS Process, In: Proceedings of World Cong. on Comp. Science and Information Eng. (March 31–April 2, 2009 LA USA), 2009, 480–483

  • [15] Rashid S., Ali S., Roy A., Rashid H., Gain-Bandwidth Adjusting Techinque of A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 μm CMOS Process, In: Proceedings of Int. Conf. on Advanced Communication Tech. (Feb. 15–18, 2009 Phoenix Park Korea), 2009, 184–188

  • [16] Matthaei G.L., Young L., Jones E., Microwave Filters, Impedance-Matching Networks and Coupling Structures, New York: McGraw-Hill, 1964.

  • [17] Tsai J.H., Chen W.C., Wang T.P., et al., A miniature Q-band low noise amplifier using 0.13 μm CMOS technology, IEEE MWCL, 2006, 16, 327–329

  • [18] Sanduleanu M.A.T., Zhang G., Long J.R., 31–34 GHz Low Noise Amplifier with On-chip microstrip Lines and Inter-stage Matching in 90nm Baseline CMOS, In: Proceedings of Radio Frequency Integrated Circuits Symp. (June 11–13, 2006 San Francisco California), 2006, 143–146

  • [19] Haque M.A., Hossain M.S., Ahmed S., Rashid H., 18.2 GHz Differential Low Noise Amplifier for On- Chip Ultra Wide Band Transceiver, In: Proceedings of IEEE Region 10 Conf. (Nov. 14–17, 2006 Hong Kong), 2006, 1–4

  • [20] Guo X., O K.K., A Power Efficient Differential 20 GHz Low Noise Amplifier With 5.3 GHz 3 dB Bandwidth, IEEE MWCL, 2005, 15, 603–605

  • [21] Floyd B., Shi L., Taur Y., Lagnado I., et al., 15-GHz wireless interconnect implemented in a 0.18 μm CMOS technology using integrated transmitters, receivers, and antennas, In: Proceedings of VLSI Symp. Circuits (June 14–16, 2001 Kyoto Japan), 2001, 155–158

  • [22] Yu Y.H., Chen Y.J.E., Heo D., A 0.6 V low power UWB CMOS LNA, IEEE MWCL, 2007, 17, 229–231

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