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Formalized Mathematics

(a computer assisted approach)

Editor-in-Chief: Matuszewski, Roman

4 Issues per year


SCImago Journal Rank (SJR) 2016: 0.207
Source Normalized Impact per Paper (SNIP) 2016: 0.315

Open Access
Online
ISSN
1898-9934
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Volume 16, Issue 4 (Jan 2008)

Issues

Stability of the 4-2 Binary Addition Circuit Cells. Part I

Katsumi Wasaki
Published Online: 2009-03-20 | DOI: https://doi.org/10.2478/v10037-008-0046-7

Stability of the 4-2 Binary Addition Circuit Cells. Part I

To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuits (GFAs) that generalized adder to have for each positive and negative weights to inputs and outputs [15]. We then successfully prove its circuit stability of the calculation outputs after four-steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.

MML identifier: FTACELL1, version: 7.9.03 4.108.1028

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About the article


Published Online: 2009-03-20

Published in Print: 2008-01-01


Citation Information: Formalized Mathematics, ISSN (Online) 1898-9934, ISSN (Print) 1426-2630, DOI: https://doi.org/10.2478/v10037-008-0046-7.

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