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it - Information Technology

Methods and Applications of Informatics and Information Technology

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Volume 58, Issue 6

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Providing fault tolerance through invasive computing

Vahid Lari
  • Corresponding author
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany Germany
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/ Andreas Weichslgartner
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany Germany
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/ Alexandru Tanase
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany Germany
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/ Michael Witterauf
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany Germany
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/ Faramarz Khosravi
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany Germany
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/ Jürgen Teich
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/ Jan Heißwolf / Stephanie Friederich
  • Karlsruhe Institute of Technology (KIT), Institute for Information Processing Technologies (ITIV), Engesserstr. 5, 76131 Karlsruhe, Germany Germany
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Published Online: 2016-10-19 | DOI: https://doi.org/10.1515/itit-2016-0022

Abstract

As a consequence of technology scaling, today's complex multi-processor systems have become more and more susceptible to errors. In order to satisfy reliability requirements, such systems require methods to detect and tolerate errors. This entails two major challenges: (a) providing a comprehensive approach that ensures fault-tolerant execution of parallel applications across different types of resources, and (b) optimizing resource usage in the face of dynamic fault probabilities or with varying fault tolerance needs of different applications. In this paper, we present a holistic and adaptive approach to provide fault tolerance on Multi-Processor System-on-a-Chip (MPSoC) on demand of an application or environmental needs based on invasive computing. We show how invasive computing may provide adaptive fault tolerance on a heterogeneous MPSoC including hardware accelerators and communication infrastructure such as a Network-on-Chip (NoC). In addition, we present (a) compile-time transformations to automatically adopt well-known redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) for fault-tolerant loop execution on a class of massively parallel arrays of processors called as Tightly Coupled Processor Arrays (). Based on timing characteristics derived from our compilation flow, we further develop (b) a reliability analysis guiding the selection of a suitable degree of fault tolerance. Finally, we present (c) a methodology to detect and adaptively mitigate faults in invasive NoCs.

Keywords: Heterogeneous MPSoC; adaptive fault tolerance; structural redundancy; network-on-chip; massively parallel processor arrays; resource-aware parallel programming

ACM CCS: Computer systems organization →Dependable and fault-tolerant systems and networks; Computer systems organization →Architectures →Parallel architectures →Multicore architectures

About the article

Vahid Lari

Dr.-Ing. Vahid Lari received his Bachelor and Master degrees in computer engineering from Isfahan University and Sharif University of Technology, Iran in 2005 and 2007, and his Doctorate degree form Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) in 2015. Currently, He is a post-doctoral researcher at the chair of Hardware/Software Co-Design, FAU.

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany

Andreas Weichslgartner

Dipl.-Ing. Andreas Weichslgartner received his Diploma degree in Information and Communication Technology from Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany in 2010. Since 2010, He is doctoral researcher at the chair of Hardware/Software Co-Design, FAU.

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany

Alexandru Tanase

Dipl.-Ing. Alexandru Tanase received his Diploma degree in computer engineering in 2006 and master degree in parallel processing in 2008 from ULBS University, Romania. Since 2011, He is a doctoral researcher at the chair of Hardware/Software Co-Design, FAU.

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany

Michael Witterauf

Dipl.-Inf. Michael Witterauf received his Diploma degree in computer engineering from Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany in 2014. Since 2014, He is a doctoral researcher at the chair of Hardware/Software Co-Design, FAU.

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany

Faramarz Khosravi

Faramarz Khosravi received his Bachelor and Master degrees in Computer Engineering from the University of Mazandaran and Sharif University of Technology, Iran in 2009 and 2011. Since 2013, he is a researcher at Hardware/Software Co-Design, FAU.

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany

Jürgen Teich

Prof. Dr.-Ing. Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern and the PhD (Dr.-Ing.) degree from the University of Saarland, Saarbrücken, Germany in 1993. Since 2003, he is appointed full professor in the Computer Science Institute, FAU holding a chair for Hardware/Software Co-Design.

Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Hardware/Software Co-Design, Cauerstr. 11, 91058 Erlangen, Germany

Jan Heißwolf

Dr.-Ing. Jan Heißwolf received his Diploma and Ph.D. in Electrical Engineering from the Karlsruhe Institute of Technology (KIT), Germany in 2009 and 2014. Currently, he is working for the Robert Bosch GmbH as an ASIC design engineer in the domain of signal processing and core IP design.

Robert Bosch GmbH, Tuebingerstr. 123, 72762 Reutlingen, Germany

Stephanie Friederich

Dipl.-Ing. Stephanie Friederich received her Diploma degree in Electrical Engineering the from Karlsruhe Institute of Technology (KIT), Germany, in 2010. Since 2010, she is a doctoral researcher at the Institute for Information Processing Technologies (ITIV), KIT.

Karlsruhe Institute of Technology (KIT), Institute for Information Processing Technologies (ITIV), Engesserstr. 5, 76131 Karlsruhe, Germany

Jürgen Becker

Prof. Dr.-Ing. Dr.h.c. Jürgen Becker received his masters degree (Dipl.-Ing.) and the PhD (Dr.-Ing.) degree from the University of Kaiserslautern, Germany in 1992 and 1997. Since 2001, he is appointed full professor and head of the Institute for Information Processing Technologies (ITIV) at the Karlsruhe Institute of Technology (KIT) and director of the Embedded Systems and Sensors Engineering (ESS) group at the Computer Science Research Center (FZI).

Karlsruhe Institute of Technology (KIT), Institute for Information Processing Technologies (ITIV), Engesserstr. 5, 76131 Karlsruhe, Germany


Accepted: 2016-09-25

Received: 2016-04-29

Published Online: 2016-10-19

Published in Print: 2016-12-28


Citation Information: it - Information Technology, Volume 58, Issue 6, Pages 309–328, ISSN (Online) 2196-7032, ISSN (Print) 1611-2776, DOI: https://doi.org/10.1515/itit-2016-0022.

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