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Journal of Electrical Engineering

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Volume 66, Issue 3 (May 2015)


Construction of Error Control Run Length Limited Codes Exploiting Some Parity Matrix Properties

Katarína Farkašová
  • Institute of Applied Informatics, Faculty of Informatics, Pan-European University, Bratislava, Slovakia
/ Peter Farkaš
  • Corresponding author
  • Institute of Telecommunications, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Slovakia
  • Email:
/ Martin Rakús
  • Institute of Telecommunications, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Slovakia
/ Eugen Rušický
  • Institute of Applied Informatics, Faculty of Informatics, Pan-European University, Bratislava, Slovakia
/ Adāo Silva
  • Telecommunications Institute, University of Aveiro, Portugal
/ Atílio Gameiro
  • Telecommunications Institute, University of Aveiro, Portugal
Published Online: 2015-07-14 | DOI: https://doi.org/10.2478/jee-2015-0030


Error control codes (ECC) as well as translation codes (TC) are used today in many different systems such as computer storages, communications systems and consumer electronic devices. ECC introduce redundancy into the encoded digital sequence in order to decrease the number of errors at output of its decoder [1]. TC introduce redundancy, in order to translate any digital sequence at the input of TC encoder to such output sequence, which fulfills constrains deduced from practical requirements. It is possible to construct codes, which have both of these properties, so called Transcontrol codes or their subclass error control run length limited (ECRLL) codes. In this manuscript a new approach to construction of EC-RLL codes is presented. The new construction is based on some parity check matrix properties of a linear binary block code from which the new EC-RLL code is obtained.

Keywords: error control codes (ECC); translation codes (TC); error control run length limited codes; modifier


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About the article

Received: 2014-12-01

Published Online: 2015-07-14

Published in Print: 2015-05-01

Citation Information: Journal of Electrical Engineering, ISSN (Online) 1339-309X, DOI: https://doi.org/10.2478/jee-2015-0030. Export Citation

© Faculty of Electrical Engineering and Information Technology, Slovak University of Technology. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License. (CC BY-NC-ND 3.0)

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