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Metrology and Measurement Systems

The Journal of Committee on Metrology and Scientific Instrumentation of Polish Academy of Sciences

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IMPACT FACTOR 2016: 1.598

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5 ps Jitter Programmable Time Interval/Frequency Generator

Paweł Kwiatkowski
  • Corresponding author
  • Military University of Technology, Faculty of Electronic, Gen. Sylwestra Kaliskiego 2, 00-908 Warsaw, Poland
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/ Krzysztof Różyc / Marek Sawicki / Zbigniew Jachna / Ryszard Szplet
Published Online: 2017-03-20 | DOI: https://doi.org/10.1515/mms-2017-0009


A new time interval/frequency generator with a jitter below 5 ps is described. The time interval generation mechanism is based on a phase shifting method with the use of a precise DDS synthesizer. The output pulses are produced in a Spartan-6 FPGA device, manufactured by Xilinx in 45 nm CMOS technology. Thorough tests of the phase shifting in a selected synthesizer are performed. The time interval resolution as low as 0.3 ps is achieved. However, the final resolution is limited to 500 ps to maximize precision. The designed device can be used as a source of high precision reference time intervals or a highly stable square wave signal of frequency up to 50 MHz.

Keywords: time interval generator; digital-to-time converter; DDS synthesizer; phase shifting; FPGA


  • [1] Rivoir, J., (2006). Full-digital time-to-digital converter for ATE with autonomous calibration. Proc. of IEEE Int. Test. Conf. 2006, Santa Clara, CA, USA, 1–10.Google Scholar

  • [2] Szplet, R., Jachna, Z., Kwiatkowski, P., Różyc. K. (2013). A 2.9 ps equivalent resolution interpolating time counter based on multiple coding lines. Meas. Sci. Technol., 24(3), 035904/1−15.Google Scholar

  • [3] Vornicu, I., Carmona-Galan, R., Rodriguez-Vazquez, A. (2016). Time interval generator with 8 ps resolution and wide range for large TDC array characterization. Analog. Integr. Cir. Sig. Process, 87(2), 181−189.Google Scholar

  • [4] Using Digitally Programmable Delay Generators. AN-260 Application Note, Analog Devices. http://www.analog.com/media/en/technical-documentation/application-notes/105895411AN-260.pdf. (1998).Google Scholar

  • [5] Alhdab, S., Mantyniemi, A., Kostamovaara, J. (2012). A 12-bit Digital-to-Time Converter (DTC) with sub-ps-level resolution using current DAC and differential switch for Time-to-Digital Converter (TDC). Proc. of IEEE I2MTC 2012., Graz, Austria, 2668−2671.Google Scholar

  • [6] Klepacki, K., Pawłowski, M., Szplet, R. (2015). Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging. Rev. Sci. Instrum., 86(2), 025111/1−7.Web of ScienceCrossrefGoogle Scholar

  • [7] Rahkonen, T., Kostamovaara, J. (1993). The use of stabilized CMOS delay line for the digitization of short time intervals. IEEE J. Solid-State Circuits, 28(8), 887−894.Google Scholar

  • [8] Suchenek, M. (2009). Picosecond resolution programmable delay line. Meas. Sci. Technol., 20(11), 117005/1−5.Google Scholar

  • [9] Abdulrazzaq, B.I., Abdul Halin, I., Kawahito, S., Sidek, R.M., Shafie, S. Yunus, N.A.M. (2016). A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance. SpringerPlus, 5(1), 1−32.Google Scholar

  • [10] Huang, H.-Y., Shen, J.-H. (2004). A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner. Proc. of IEEE AP ASIC 2004, Fukuoka, Japan, 76−79.Google Scholar

  • [11] Okayasu, T., Suda, M., Yamamoto, K., Kantake, S., Sudou, S., Watanabe, D. (2006). 1.83ps-resolution CMOS dynamic arbitrary timing generator for > 4 GHz ATE applications. Proc. of IEEE ISSCC 2006, San Francisco, CA, United States, 522−511.Google Scholar

  • [12] Carbone, P., Kiaei, S., Xu, F. (2014). Design, modelling and testing of data converters. Berlin, Germany: Springer-Verlag, ch. 7.Google Scholar

  • [13] Kwiatkowski, P., Jachna, Z., Różyc, K., Kalisz, J. (2012). Accurate and low jitter time-interval generators based on phase shifting method. Rev. Sci. Instrum., 83(3), 034701/1−4.CrossrefWeb of ScienceGoogle Scholar

  • [14] Suchenek, M., Starecki, T. (2012). Programmable pulse generator based on programmable logic and direct digital synthesis. Rev. Sci. Instrum., 83(12), 124704/1−4.CrossrefWeb of ScienceGoogle Scholar

  • [15] Chen, Y.-Y., Huang, J.-L., Kuo, T., Huang, X.-L. (2015). Design and implementation of an FPGA-based data/timing formatter. J. Electron. Test., 31(5−6), 549−559.Web of ScienceCrossrefGoogle Scholar

  • [16] Yao, Y., Wang, Z., Lu, H., Chen, L., Jin, G. (2016). Design of time interval generator based on hybrid counting method. Nucl. Instrum. Methods Phys. Res., Sect. A, 832, 103−107.Google Scholar

  • [17] Kalisz, J., Poniecki, A., Różyc, K. (2003). A simple, precise, and low jitter delay/gate generator. Rev. Sci. Instrum., 74(7), 3507−3509.CrossrefGoogle Scholar

  • [18] Chen, P., Chen, P.-Y., Lai, J.-S., Chen, Y.-J. (2010). FPGA vernier digital-to-time converter with 1.58 ps resolution and 59.3 minutes operation range. IEEE Trans. Circuits Syst. I, Reg. Papers, 57(6), 1134−1142.Google Scholar

  • [19] Song, Y., Liang, H., Zhou, L., Du, J., Ma, J., Yue, Z. (2011). Large dynamic range high resolution digital delay generator based on FPGA. Proc. of ICECC 2011, Zhejiang, China, 2116−2118.Google Scholar

  • [20] Miari, L., Antonioli, S., Labanca, I., Crotti, M., Rech, I., Ghioni, M. (2015). Eight-channel fully adjustable pulse generator. IEEE Trans. Instrum. Meas., 64(9), 2399−2408.Google Scholar

  • [21] Kwiatkowski, P., Szplet, R., Jachna, Z., Różyc, K. (2016). A time digitizer based on multiphase clock implemented in FPGA device. Proc. of EBCCSP 2016, Cracow, Poland.Google Scholar

  • [22] Optimizing clock synthesis in small cells and heterogeneous networks. White Paper, Silicon Laboratories. https://www.silabs.com/Support%20Documents/TechnicalDocs/Silicon%20Labs%20Next-Generation%20DSPLL%20Technology%20White%20Paper%20-%20June%202015.pdf. (Jun. 2015)Google Scholar

  • [23] 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer. Datasheet, Analog Devices. http://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf. (May 2012).Google Scholar

  • [24] ISE In-Depth Tutorial. User Guide UG695, v.14.1, Xilinx. http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ise_tutorial_ug695.pdf. (Apr. 2012).Google Scholar

  • [25] Keysight Technologies Infiniium 90000 Series Oscilloscopes. Datasheet, Keysight Technologies. http://literature.cdn.keysight.com/litweb/pdf/5989-7819EN.pdf. (2015).Google Scholar

  • [26] Szplet, R., Kwiatkowski, P., Jachna, Z., Różyc, K. (2016). An eight-channel 4.5-ps precision timestamps-based time interval counter in FPGA chip, IEEE Trans. Instrum. Meas., 65(9), 2088−2100.Google Scholar

About the article

Received: 2016-07-20

Accepted: 2016-09-29

Published Online: 2017-03-20

Published in Print: 2017-03-01

Citation Information: Metrology and Measurement Systems, Volume 24, Issue 1, Pages 57–68, ISSN (Online) 2300-1941, DOI: https://doi.org/10.1515/mms-2017-0009.

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© 2017 Polish Academy of Sciences. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License. BY-NC-ND 3.0

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