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Ultracompact on-chip photothermal power monitor based on silicon hybrid plasmonic waveguides

Hao Wu
• Centre for Optical and Electromagnetic Research, State Key Laboratory for Modern Optical Instrumentation, Zhejiang Provincial Key Laboratory for Sensing Technologies, Zhejiang University, Hangzhou 310058, China
• JORCEP Joint Research Center of Photonics of the Royal Institute of Technology (Sweden) and Zhejiang University, Hangzhou 310058, China
• Other articles by this author:
/ Ke Ma
• Centre for Optical and Electromagnetic Research, State Key Laboratory for Modern Optical Instrumentation, Zhejiang Provincial Key Laboratory for Sensing Technologies, Zhejiang University, Hangzhou 310058, China
• JORCEP Joint Research Center of Photonics of the Royal Institute of Technology (Sweden) and Zhejiang University, Hangzhou 310058, China
• Other articles by this author:
/ Yaocheng Shi
• Centre for Optical and Electromagnetic Research, State Key Laboratory for Modern Optical Instrumentation, Zhejiang Provincial Key Laboratory for Sensing Technologies, Zhejiang University, Hangzhou 310058, China
• JORCEP Joint Research Center of Photonics of the Royal Institute of Technology (Sweden) and Zhejiang University, Hangzhou 310058, China
• Other articles by this author:
/ Lech Wosinski
• JORCEP Joint Research Center of Photonics of the Royal Institute of Technology (Sweden) and Zhejiang University, Hangzhou 310058, China
• School of Information and Communication Technology, Royal Institute of Technology, 164 40, Kista, Sweden
• Other articles by this author:
/ Daoxin Dai
• Corresponding author
• Centre for Optical and Electromagnetic Research, State Key Laboratory for Modern Optical Instrumentation, Zhejiang Provincial Key Laboratory for Sensing Technologies, Zhejiang University, Hangzhou 310058, China
• JORCEP Joint Research Center of Photonics of the Royal Institute of Technology (Sweden) and Zhejiang University, Hangzhou 310058, China
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• Other articles by this author:
Published Online: 2017-01-20 | DOI: https://doi.org/10.1515/nanoph-2016-0169

Abstract

We propose and demonstrate an ultracompact on-chip photothermal power monitor based on a silicon hybrid plasmonic waveguide (HPWG), which consists of a metal strip, a silicon core, and a silicon oxide (SiO2) insulator layer between them. When light injected to an HPWG is absorbed by the metal strip, the temperature increases and the resistance of the metal strip changes accordingly due to the photothermal and thermal resistance effects of the metal. Therefore, the optical power variation can be monitored by measuring the resistance of the metal strip on the HPWG. To obtain the electrical signal for the resistance measurement conveniently, a Wheatstone bridge circuit is monolithically integrated with the HPWG on the same chip. As the HPWG has nanoscale light confinement, the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. The compactness helps to improve the thermal efficiency and the response speed. For the present power monitor fabricated with simple fabrication processes, the measured responsivity is as high as about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

This article offers supplementary material which is provided at the end of the article.

1 Introduction

An optical power monitor often plays an important role to collect feedback information for the management and control in optical systems for communication [1], [2], [3] as well as sensing [4], [5], [6]. For example, in a “self-configuring” optical communication system, power monitoring is usually needed for controlling the power level of optical signals to minimize the impact of environmental variations as well as mutual crosstalk effects when some channels are added or dropped [2]. For optical sensing, which is becoming more and more attractive for numerous applications, including environment monitoring [7], [8], [9] and human health [10], [11], [12], power monitors are also indispensable for detecting the power variation of the optical signal.

To realize optical power monitoring, various photodetectors have been developed successfully in the past decades [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24]. Among them, a photodetector on silicon is one of the most popular options regarding the unique advantages of silicon material (e.g. low cost, easy fabrication, high performances, and CMOS compatibility). Pure silicon photodetectors have been developed very well and have shown excellent performances in the short wavelength range (<1.1 μm), where silicon has a high absorption coefficient [13]. For the operation wavelength longer than 1.1 μm [e.g. near-infrared (IR) or mid-IR light], silicon becomes transparent with almost zero absorption and one should introduce some other materials with a high absorption coefficient in the wavelength range of >1.1 μm [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24]. Particularly, for the optical fiber communication window about 1.55 μm, III-V materials (e.g. InP and GaAs) and germanium are very popular because of their high absorption coefficients. High-performance photodetectors have been realized with the hybrid platforms of III-V/Si [14], [15] and Ge/Si [17], [18]. The responsivity is higher than 1 A/W [16], [17], [18], and the 3dB bandwidth is even more than 100 GHz [14], [15], which is very useful for high-speed optical fiber communication.

However, the operation wavelength range for a semiconductor photodetector is usually limited by the bandgap of the semiconductor material. For example, the III-V/Si or Ge/Si photodetectors are not available for the mid-IR wavelength range, which is of great interest for numerous applications, including optical sensing, because the mid-IR region (2–7 μm) is often referred as the “fingerprint region” due to the uniquely identifiable absorption spectra for many molecules [8], [25], [26], [27]. To enable the photodetection of mid-IR light, it is also possible to introduce some special low-bandgap semiconductor materials [21], [22], [23], [24]. However, they are often expensive and usually require to be operated at low temperatures (<100 K) to depress the thermal noise [21], [22], [23], [24]. Furthermore, it is still not easy to directly grow a different semiconductor material (including III–V or Ge) on a silicon substrate due to the lattice mismatch between them, and special fabrication techniques are needed, including direct bonding [28], adhesive bonding [29], and BCB bonding [30].

Alternatively, the photothermal effect has been used as a low-cost and convenient way to detect the light with wavelength ranging from UV to mid-IR [31], [32], [33], [34], [35], [36], [37], [38], [39]. When light is absorbed by an absorber, the temperature of the absorber increases and the temperature variation can be measured easily using various techniques [34], [36]. For example, when the metal is chosen as the light absorber, the resistance of a metal strip changes as the temperature increases due to the thermal resistance effect, and the resistance can be monitored accurately by measuring the voltage drop of the metal resistance. In this case, the responsivity is usually given with the unit of V/W (or mV/mW). It is well known that surface plasmon polariton (SPP) can be supported at the metal/dielectric interface and SPP modes usually have a significant field enhancement as well as light localization at the metal/dielectric interfaces. This makes contributions to the ultrastrong light confinement [40], [41], [42], [43], [44], [45], [46] as well as the enhancement of the light-matter interaction [47] (e.g. light emission [48], [49], [50], light absorption [51], [52], [53], and optical sensing [53], [54]). In this case, the photothermal effect in plasmonic nanostructures is expected to be enhanced. As the metal strip can be fabricated very easily and compatibly with regular photonic integrated circuits, it is convenient to develop on-chip photothermal power monitor with metal structures on various substrates. In 2005, Bozhevolnyi et al. demonstrated the first on-chip photothermal power monitor with a long-range surface plasmonic waveguide (LRSPW) [37], which consists of an 8 μm-wide and 1 mm-long metal strip buried in a polymer layer. The measured responsivity is about 0.15 mV/mW (at a bias voltage of 2 V), which is relatively low due to the large footprint [37]. In 2011, Kumar et al. demonstrated an improved power monitor with a dielectric-loaded surface plasmonic waveguide (DLSPW) [38]. A further improvement for the DLSPW power monitor was demonstrated in 2013 [39] by introducing a thermal insulator layer based on Cytop whose thermal conductivity coefficient is as low as κ=0.12 W/(m×K). A Wheatstone bridge circuit was also integrated on the same chip to improve the measurement precision, and the whole footprint is 46×46 μm2 [39]. This improved power monitor has an enhanced responsivity as high as ~6.4 μV/μW at a bias voltage of 245 mV [39]. However, the maximal input power allowed is limited due to the low melting point of Cytop and Cyclomer, which were used for the substrate and the waveguide. This power monitor is also not compatible with silicon photonics (which is very popular for many applications [55], [56], [57], [58]).

As an alternative option, we theoretically proposed the basic concept of realizing compact power monitors with high responsivity using a single silicon hybrid plasmonic waveguide (HPWG) in our previous conference paper [59]. The silicon HPWG, which usually has a metal strip, a silicon core, and an silicon oxide (SiO2) insulator layer between them, was proposed as a novel waveguide with nanoscale light confinement as well as relatively long propagation distance [46] and has become very popular for integrated nanophotonics in the past years [60], [61], [62], [63], [64], [65]. Meanwhile, plasmonic structures and waveguides are also promising candidates for the application at mid-IR wavelength [66], [67]. In this paper, we design and demonstrate a photothermal power monitor realized with a silicon HPWG for the first time. The present power monitor is integrated with an improved Wheatstone bridge circuit on the same chip so that one can read the electrical signal conveniently. Owing to the very strong light confinement of silicon HPWGs used here [46], the footprint of the present power monitor is shrunk greatly, which then helps to improve the photothermal efficiency and the response speed [68]. Particularly, the SiO2 insulator layer sandwiched between the silicon layer and the metal strip also plays a role as a thermal insulator to prevent the heat dissipation. As an example, the power monitor demonstrated in this paper is realized with a 300-nm-wide and 3-μm-long silicon HPWG, which is the smallest photothermal power monitor reported until now. The measured responsivity for the present power monitor is about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

2 Device analysis and fabrication

Figure 1A shows the three-dimensional schematic configuration of the proposed power monitor based on a silicon HPWG whose cross-section is shown in Figure 1B. The silicon HPWG has a metal strip, which sits on top of the silicon core waveguide surrounded by SiO2. This metal strip is designed to be narrower slightly than the waveguide under it to make the overlay fabrication process relatively easy. Another three metal strips are placed at the side of the silicon HPWG so that a Wheatstone bridge electrical circuit is formed and monolithically integrated on the same chip. The silicon HPWG is connected directly with an SOI nanowire waveguide in the front end regarding that their butt-coupling efficiency is relatively high (~85%) [69]. In this way, light can be coupled easily into the chip through a focused waveguide grating coupler connected to the SOI nanowire waveguide. When light is coupled from the fiber to the chip and propagates along the silicon HPWG, light absorption from the metal strip occurs and heat is generated. As a result, the resistance Rm of the metal strip increases, which can be then measured accurately and directly in an electrical way. Therefore, an on-chip optical power monitor can be realized. This device is designed optimally to work for TM polarization. As the TE polarization mode is also supported in the present waveguide and efficient metal absorption happens, the present power monitor works for TE polarization mode, whereas the responsivity is polarization dependent.

Figure 1:

Schematic configuration of the proposed power monitor and the simulated photothermal effect.

(A) Three-dimensional schematic configuration of the proposed silicon HPWG power monitor integrated with the Wheatstone bridge circuit. Inset: detail of connection between metal strips and electrodes. (B) Cross-section of the silicon HPWG in the absorption region. (C) Calculated distribution of temperature increase in the whole structure when 1 mW optical power is received. Here, the increased temperature distribution in the metal strips on the silicon HPWG as well as on the substrate is also shown. (D) Calculated average temperature variations $\left(\overline{\Delta {T}_{R1}},\text{\hspace{0.17em}}\overline{\Delta {T}_{R\text{2}}},\text{\hspace{0.17em}}\overline{\Delta {T}_{R\text{3}}},\text{\hspace{0.17em}and\hspace{0.17em}}\overline{\Delta {T}_{R\text{m}}}\right)$ of the four metal strips (R1, R2, R3, and Rm) as the input optical power Pin increases. Here, the parameters are chosen as wm=400 nm, wSi=350 nm, hSiO2=50 nm, hSi=225 nm, hm=80 nm, and lm=10 μm.

Figure 1C shows the calculated distribution of temperature increase in the whole structure when the input optical power Pin is 1 mW as an example. The thermal simulation was done with the time-domain finite element method. Here, the geometrical parameters are chosen as wm=400 nm, wSi=350 nm, hSiO2=50 nm, hSi=225 nm, hm=80 nm, and lm=10 μm. The heat capacity, density, and thermal conductivity for the materials used are shown in Table 1. It can also be seen that the longitudinal metal strip on the silicon HPWG is heated significantly due to the light absorption, whereas the adjacent perpendicular metal strip is heated gently due to the thermal conduction. The temperature variation is not uniform spatially, as the absorption is nonuniform along the propagation distance z (see Figure 1C and Section 1 in Supplemental Material). Apparently, the optical power absorbed by the metal strip to generate heat decreases exponentially along the propagation length in z direction, and there is a part of the heat dissipated due to the heat conduction to the surrounding regions (e.g. the SiO2/Si layers beneath), that is, P(z)=Pinexp(-aabsz)=Pmetal+Pd, where Pin is the input optical power, aabs is the absorption coefficient, Pmetal is the part of Pin that turns into the heat of metal strip, and Pd is the part of Pin that is heat dissipation. Therefore, it is expected that the temperature variation ΔT(z) of the metal strip decreases along the propagation distance z, as shown in Figure 1C (see also Section 1 in Supplemental Material). However, the temperature variation ΔT(z=0) at the front end (z=0) of the metal strip becomes reduced slightly (see Figure 1C) because there is some heat dissipation in the -z direction due to the SOI nanowire waveguide connected at the front end of the silicon HPWG.

Table 1:

Heat capacity, density, and thermal conductivity of the materials used for calculation [70].

Nevertheless, to simplify the estimation of the resistance Rm of the metal strip, we define a parameter (i.e. average temperature variation $\overline{\Delta T}$) for each metal strip (see Section 2 in Supplemental Material). Figure 1D shows the calculated average temperature variation $\overline{\Delta T}$ for the four metal strips as the input optical power Pin varies. It can be seen that the metal strip on the silicon HPWG is much hotter than the other three metal strips, and the temperature variation of the metal strip is almost proportional to the launched power Pin, that is,

$ΔT¯≈ηPin,$(1)

where η is a constant. With the average temperature variation $\overline{\Delta T},$ the resistance Rm of the metal strip can be calculated with the following simplified formula [71]:

$Rm=Rm0(1+αΔT¯),$(2)

where Rm0 is the dark resistance when there is no light incident and α is the temperature coefficient of resistivity (TCR) that depends on the material property [71], the thin-film thickness [72], and the roughness of metal films [73]. As it is known, the TCR is a function of the temperature and can be approximated as a constant over a reasonable temperature range [71]. The TCR for most metals is usually a positive value between 0.0038 and 0.005 K−1 [74].

To achieve an accurate measurement for the increase of the resistance Rm due to light absorption, a Wheatstone bridge electrical circuit is integrated on the same chip, as shown in Figure 1A. This Wheatstone bridge circuit has four metal strips with identical resistances. The metal strip on the top of the silicon HPWG is the variable element (due to the light absorption) for a Wheatstone bridge circuit. The other three metal strips (resistances) are placed at the side of the silicon HPWG as the fixed elements of the Wheatstone bridge circuit (see Figure 1A). Here, we move the connection position away from a silicon HPWG (as shown by the inset in Figure 1A) to minimize the undesired thermal crosstalk to the three fixed metal-strip elements. There are four metal pads (B+, S+, B, and S) used to connect to the external electrical circuit (including the electrical power source). When applying an external voltage Vbias between point B+ and point B, the voltage Vsignal between point S+ and point S is related to the resistance Rm to be measured as follows:

$Vsignal=Vbias (RmRm+R3−R1R1+R2),$(3)

where R1, R2, R3, and Rm are the four resistances in the Wheatstone bridge, as shown in Figure 1A. To balance the bridge and maximize the responsivity, the four resistances are usually desired to be equal in the dark case (without light). One should note that these resistances might be different slightly in practice, although they are designed to be identical. Fortunately, this can be calibrated in the measurement so that such a slight difference of these resistance has little influence on the responsivity. With the approximation of R1=R2=R3=Rm0, where Rm0 is the resistance without light, Eq. (3) can be simplified as

$Vsignal=Vbias2αΔT¯2+αΔT¯,$(4)

Usually, the TCR for most metal materials is very small (e.g. α~10−3 for gold, aluminum, platinum, and silver [74]); thus, one has $\alpha \overline{\Delta T}$<<2 if the average temperature variation $\overline{\Delta T}$ is not high. For example, for the present optical power monitor with the parameters wm=400 nm and lm=15 μm, the calculated temperature variation $\overline{\Delta T}$ is ~26.9°C when there is an input optical power of 1 mW. In this case, the output voltage Vsignal is rewritten approximately in the following simplified form:

$Vsignal=VbiasαΔT¯4=VbiasαηPin4,$(5)

It can be seen that the output signal Vsignal is linearly proportional to the optical power Pin, which makes the measurement and characterization very convenient.

The fabrication processes were started on an SOI wafer with a 250-nm-thick top silicon layer and a 2-μm-thick buried-oxide layer. The SOI nanowire waveguides together with the focused waveguide grating couplers were made with an E-beam lithography and an ICP (inductive coupled plasma) etching process. A dry thermal-oxidization process under 1050°C was then followed to form a ~50-nm-thick SiO2 layer at the sidewalls as well as the top surface of the silicon core. This 50-nm-thick SiO2 layer acts as the low-index nanolayer (between the metal strip and the silicon core) in the silicon HPWG. Finally, another E-beam lithography process and a lift-off process were followed to make the metal strips and the electrodes. The metal thickness was controlled very precisely to be about 80 nm by adjusting the time of the metal deposition. Here, we choose platinum as the metal for the silicon HPWG as well as the electrodes because of its excellent chemical stability in air when operating at high temperature and relatively low thermal conductivity [κ=71.6 W/(m K)] [70]. Moreover, platinum has efficient light absorption in the silicon HPWG so that the power monitor can be very compact. The low thermal conductivity of platinum also helps reduce the thermal dissipation/crosstalk due to the thermal conduction from the heated metal strip to the metal connector and pads. The thicknesses of both the SiO2 nanolayer and the metal strip were appropriately designed to balance the performance and fabrication, as discussed in Supplemental Material.

To determine the temperature dependence of the resistance of the metal strip, we designed and fabricated some test structures with platinum strips situated on SOI nanowire waveguides on the same chip, as shown in Figure 2A. The resistance of the platinum strip is then measured as the temperature Tchip increases using an external electrical heater on the substrate. In this way, the temperature is uniform along the metal strip. Figure 2B shows the measured resistance for the platinum strip as the temperature Tchip at the top-surface of the chip increases. It can be seen that the resistance increases almost proportionally as the temperature increases. From the measurement results shown in Figure 2B, the estimated TCR is about 0.00156 K−1, which is smaller than that (~0.0039 K−1) of the bulk platinum material. This difference should be due to the dependence of the TCR on the size [72] and the roughness of the metal film [73]. We also measured the dependence of the metal-strip resistance on the input optical power Pin when light is coupled into the SOI nanowire waveguide through a grating coupler (see Figure 2A). From the simulation and measurement results shown in Figure 2C, it can be seen that the measured resistance is proportional to the input optical power, which agrees very well with the prediction from Eqs. (1) and (2).

Figure 2:

A photothermal power monitor based on a single HPWG.

(A) Scanning electron microscopy (SEM) pictures of the silicon HPWG with electrodes to measure the resistance of metal strip. Inset: details of the test structure. (B) Measured resistances for the metal strip with different widths (wm=300, 400, and 500 nm) when the chip surface is at different temperatures Tchip (which was controlled by a TEC temperature controller). (C) Measured and calculated resistances of the metal strips with different widths as the input optical power Pin increases. Here. lm=15 μm. Cal, simulation; MEAS, measurement.

3.1 Measurement setup

To characterize the fabricated power monitors, we have built a test set-up, as shown in Figure 3A. A tunable laser (Agilent 81940A) was used as the light source whose wavelength ranges from 1520 to 1630 nm. A highly sensitive photodetector (Agilent 81618A) was used to collect the residual light exiting from the output grating coupler (as shown in Figure 3B), which helps the alignment of the input/output fibers. For the external electrical link, two Keithley-2400 source meters were employed here. One was to apply a bias voltage Vbias to the pads (B+ and B) and the other one was applied to the pads (S+ and S) for measuring the output signal Vsignal. For the temporal response measurement, light from the laser source is first modulated at a frequency of 1 kHz with an internal modulator and then coupled into the chip through the grating coupler. The fabricated grating couplers on the same chip have a fiber-chip coupling efficiency of ~20% in the wavelength range from 1520 to 1560 nm. A low-pass filter (<100 kHz) integrated with an electrical amplifier (SRS SR560) was used to filter out the high-frequency noise and amplify the signal. Finally, the electrical signal output Vsignal was then analyzed with an oscilloscope (Agilent DSO1022A).

Figure 3:

Measurement setup.

(A) Test set-up to characterize the responsivity, dynamic range, and response speed of the fabricated optical power monitor. (B) Microscope graph of the fabricated power monitor along with focused grating couplers and metal pads for testing. (C) SEM picture of the fabricated optical power monitor integrated with a Wheatstone bridge circuit.

3.2 Responsivity

Figure 4A shows the measured and calculated results for the responsivity of the fabricated power monitors with different widths and lengths for the metal strips. The calculated responsivity is slightly larger than the measured one mainly because the scattering loss of the silicon HPWG as well as the connection loss between the SOI nanowire waveguide and the silicon HPWG is ignored in the calculation model. It can be also seen that the responsivity first increases and then decreases as the metal-strip length increases, which can be explained as follows. For the present case, the absorption coefficient of the silicon HPWG is about aabs=3 dB/μm. Obviously, there is only a part of optical power absorbed when the length lm is very short (e.g. ~2 μm) and the back end of the silicon HPWG is also heated notably. Consequently, there is some notable heat dissipation at not only the frond end but also the back end of the silicon HPWG (see the insets in Figure S1A in Supplemental Material). This heat dissipation reduces the temperature variation of the silicon HPWG. In contrast, when the length lm increases, the optical power is absorbed more and the temperature increase at the back end of the silicon HPWG becomes less, which results in less heat dissipation at the back end. As a result, the temperature of the metal strip becomes higher (see Figure S1A in the Supplemental Material), which might enhance the average temperature variation $\overline{\Delta T}$ and the responsivity accordingly. However, when the length lm increases further (e.g. lm>5 μm), the temperature increase at the back end becomes much lower than that at the front end because much lower optical power is absorbed. In this case, the average temperature variation $\overline{\Delta T}$ decreases as the length lm increases [see the definition given by Eq. (S7) in Supplemental Material], which results in a reduced responsivity, as shown in Figure 4A. Figure 4A also shows the measured responsivities for the case with different metal strip widths (i.e. wm=300, 400, and 500 nm). It can be seen that higher responsivity is achieved when choosing a narrower metal strip. The measured maximum responsivities are about 17.7, 14.5, and 11.7 mV/mW for the cases with wm=300, 400, and 500 nm, respectively, when lm=5 μm and Vbias=2 V. This is because of the fact that a narrower silicon HPWG has higher absorption loss [46] as well as smaller heating volume.

Figure 4:

The responsivities.

(A) Measured and calculated responsivities of the power monitors operating at Vbias=2 V as the metal-strip length lm varies (here, wm=300, 400, and 500 nm). (B) Responsivity of the power monitor with wm=400 nm and lm=15 μm as the bias voltage Vbias varies. Here, the input optical power is Pin=1 mW.

The dependence of the responsivity on the bias voltage is also characterized. Figure 4B shows the measured responsivity of the optical power monitor with wm=400 nm and lm=15 μm when operating at different bias voltages Vbias. It can be seen that the voltage Vsignal is linearly proportional to Vbias, as expected from Eq. (5) because one has $\alpha \overline{\Delta T}$<<2 for the present case with Pin=~1.0 mW and the corresponding temperature variation $\overline{\Delta T} = 26.9°\text{C}.$ When the bias voltage Vbias increases further, higher responsivity is obtainable according to Eq. (5). On the contrary, it will cause higher dark current Idark and thus higher power consumption (which is given by Pe_dark=VbiasIdark=V2bias/R). In this case, all of the metal strips for the Wheatstone bridge circuit become hotter, which will reduce the TCR and the responsivity decreases slightly [71]. Therefore, one should make a trade-off when choosing a bias voltage.

3.3 Temperature dependence and dynamic range

According to Eq. (4), the responsivity of the present power monitor is insensitive to the variation of the environmental temperature because all the four resistances vary identically when the chip is heated or cooled uniformly. Figure 5A shows the simulated and measured results for the dependence of the responsivity of the power monitor on the variation of the temperature Tchip of the chip, which is heated uniformly by a thermoelectric cooler (TEC). Here, the power monitor is with wm=400 nm and lm=15 μm. The bias voltage is chosen as Vbias=1 and 2 V, respectively. It can be seen that the measured responsivity of the power monitor changes very little as predicted when the chip temperature Tchip varies from 15°C to 100°C. The slight responsivity variation observed in Figure 5A is due to the slight variation of the contact between the probes and the metal pads at different temperatures and the slight temperature dependence of the TCR [71].

Figure 5:

The temperature stability and the dynamic range.

(A) Measured and calculated responsivity under different temperatures Tchip controlled by a TEC when operating with Vbias=1 and 2 V. (B) Measured and calculated electrical signal Vsignal of the power monitor operating at Vbias=2 V as the input optical power Pin increases from ~0.9 μW to ~2.85 mW. (C) Calculated highest temperatures Tmax in the metal strip as the input optical power Pin increases. Here, wm=400 nm and lm=15 μm. The bias voltage is chosen as Vbias=1 and 2 V.

To characterize the dynamic range of the present optical power monitor, the response voltage Vsignal is measured as the input optical power Pin is adjusted with an optical attenuator, as shown in Figure 5B, which agrees very well with the theoretical result calculated with Eq. (5). The small divergence between the experimental and theoretical results might result from the temperature dependence of the TCR and the measurement errors. Here, the bias voltage Vbias=2 V, the device parameters are wm=400 nm, and lm=15 μm. It can be seen that the response voltage Vsignal is proportional to the input optical power varying from 0.9 μW to 2.85 mW. Correspondingly, the dynamic range for the optical power Pin is as large as ~35 dB. The sensitivity (i.e. the detection limit for low power) in our measurement is restricted partially by the dynamic range (~20 dB) of optical attenuator and the sensitivity of the source meter (Keithley 2400) used. The thermal fluctuation contributes dominantly to the noise and one can estimate the sensitivity (detection limit) of the optical power meter in theory with the following formula [37], [75]:

$VN2¯=16kTRΔf,$(6)

where k is the Boltzmann’s constant, T is the environmental temperature (e.g. T=~300 K) of the power monitor, s is the equivalent resistance of Wheatstone bridge circuit (e.g. R=~620 Ω when wm=300 nm and lm=3 μm), and ∆f is the measurement bandwidth that typically is ~1 kHz for measuring the thermal effect in plasmonic structures [37]. Hence, the estimated theoretical sensitivity of the optical power monitor is ~13 nW at a bias voltage of 2 V. It is expected that the sensitivity can be improved for low-power detection if one can further suppress the noise.

The maximal optical power allowed to be detected by the power monitor is limited by a certain temperature beyond which the metal strip breaks. As shown in Figure 1C, the temperature variation profile ΔT(z) is not uniform along the metal strip and one observes the highest temperature at the position at z0=1 μm. Figure 5C shows the calculation results for the highest temperature Tmax in the metal strip of the silicon HPWG when operating at Vbias=1 and 2 V, as the optical power increases. When operating with a higher bias voltage, the temperature becomes higher slightly due to the electrical heating (P=V2bias/R). Therefore, one should choose lower bias voltage to enable the detection for higher optical power. However, the responsivity is reduced accordingly. One should realize that the metal strip is much hotter than the silicon core (see Figure S1B in Supplementary Material), and the highest temperature Tmax increases linearly as the input optical power Pin increases. For example, for the case of Vbias=1 V, the highest local temperature in the metal strip is 940°C in theory when Pin=10 mW. With such a high temperature, the metal strip might be broken due to the oxidization or fusion. We did observe that the metal strip was broken when the input optical power is >10 mW in our experiment. The limit of maximum input power can be increased by optimizing the waveguide dimension to make the temperature distributed uniformly.

To achieve a higher upper limit for the input optical power, one can choose a thicker SiO2 insulator layer in the silicon HPWG; thus, less optical mode field interacts with the metal absorber, which thus has a lower absorption coefficient (see Figure S2A in Supplemental Material). In this case, a longer absorption length is needed for the silicon HPWG; thus, the heating volume increases. As a result, the highest temperature Tmax could become less (see Figure S2B in Supplemental Material). However, the average temperature variation and the responsivity are also reduced if the SiO2 insulator layer is too thick (e.g. hSiO2>0.3 μm). Another potential approach is introducing a special tapered HPWG so the light absorption and heating is uniform along the propagation distance, which is similar to the high-power III–V photodiodes with tapered absorption region introduced previously [76].

3.4 Rise time

Figure 6A shows the measured temporal rise time of the optical power monitor with wm=400 nm to a pulsed optical input signal at a frequency of 1 kHz when the lengths are chosen as lm=3 and 15 μm, respectively. Here, the bias voltage Vbias=2 V and the optical power Pin=3 mW. For this measurement, to filter out the high-frequency noise from DC probes and amplify the signal, we used a low-pass filter integrated with electrical amplifier (SRS SR560) connected to the oscilloscope (Agilent DSO1022A). From Figure 6A, it can be seen that the rise times are about 3.1 and 3.8 μs, respectively. As a comparison, we also calculate the rise time for the present optical power monitors with different lengths lm (ranging from 2 to 50 μm), as shown in Figure 6B. It can be seen that the rise time increases slightly as the length lm increases, and the rise time does not almost change when lm>10 μm.

Figure 6:

Temporal responses.

(A) Measured electrical temporal responses for an input optical signal with a modulation frequency of 1 kHz when Vbias=2 V. The length is chosen as lm=3 and 15 μm, respectively. Insets: rising edges. (B) Calculated electrical temporal rise time of the power monitor with different lengths lm. Here, wm=400 nm.

3.5 Wavelength dependence

Figure 7A shows the wavelength dependence of the measured and simulated responsivities of an optical power monitor with wm=400 nm and lm=15 μm when operating at different bias voltages (i.e. Vbias=1 and 2 V). The measured wavelength range is from 1520 to 1630 nm, which is limited by the tuning range of the laser as well as the bandwidth of the grating couplers. The simulated and measured results show that the responsivity is wavelength insensitive, which is expected as the metal absorption is very broad band (from the visible light to the mid-IR light) [77]. We also calculated the wavelength dependence of the absorption in the silicon HPWG when the wavelength ranges from 1 to 8 μm. The parameters are wSi=400 nm, hSi=225 nm, hSiO2=50 nm, wm=400 nm, and hm=80 nm. Figure 7B shows the calculated absorption efficiency for the silicon HPWGs with lm=5 and 10 μm. It can be seen that the absorption is efficient and very flat as a function of wavelength. Here, we do not include the wavelength range of λ>8 μm because silicon dioxide becomes very lossy. When choosing HPWGs with different dielectric material systems (e.g. Ge-on-Si systems [78]), the HPWG-based optical monitor can also work for longer wavelength, which is attractive for many applications.

Figure 7:

Wavelength dependence.

(A) Wavelength dependence of the responsivity of the fabricated optical power monitor with lm=15 μm when Vbias=1 and 2 V. (B) Wavelength dependence of the metal absorption in a 5- and 10-μm-long metal strip. Here, wm=400 nm.

4 Conclusion

In conclusion, we have proposed and demonstrated an ultracompact on-chip photothermal power monitor based on silicon HPWGs. Wheatstone bridge has been integrated with the HPWG-based power monitor on the same chip so that the electrical signal has been obtained conveniently. Platinum was chosen as the metal for the HPWG and the electrodes. The length of the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. Such a small footprint helps realize a dense optical monitor array when needed. The distance between the adjacent elements in the array should be large enough to avoid the thermal crosstalk. For the present design, fortunately, the thermal crosstalk should be low because the air upper-cladding and the SiO2 under-cladding can prevent the undesired thermal conduction from the adjacent elements very well. Furthermore, the design with a Wheatstone bridge circuit also helps minimize the influence due to the thermal crosstalk. The small footprint also helps improve the thermal efficiency and the response speed. For the present power monitor, the measured responsivity is as high as 17.7 mV/mW at a bias voltage of 2 V. The power dynamic range is as large as 35 dB and the rise time is about 3.1 μs. In particular, the present power monitor has a very flat response covering the wavelength range from 1.3 to 7.8 μm. It is possible to be extended for operating in the wavelength range beyond (e.g. >8 μm) using other material platforms (e.g. SiN or Ge-on-Si). The present power monitor should be useful for optical spectrum analysis in the near/mid-IR biochemistry field. This ultracompact photothermal power monitor is readily to be arrayed.

Supplementary material: Detailed information about the simulated temperature distribution T(x,y,z), calculation of the average temperature variation $\overline{\Delta T}$ in the metal strip, dependence of the performances on the SiO2 thickness hSiO2, and dependence of the performances on the thickness hm of the metal strip is described.

Acknowledgments

This work was supported by NSFC projects (11374263, 61422510, and 61431166001), and National Key Research and Development Plan (2016YFB0402502). The authors acknowledge valuable discussions with Dr. Xiaowei Guan, Prof. Lars Thylén, and Xu Sun about the design of HPWGs. The authors acknowledge the valuable suggestions on the fabrication process from Sitao Chen.

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Supplemental Material:

Revised: 2016-11-09

Accepted: 2016-11-16

Published Online: 2017-01-20

Citation Information: Nanophotonics, Volume 6, Issue 5, Pages 1121–1131, ISSN (Online) 2192-8614,

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