Jump to ContentJump to Main Navigation
Show Summary Details
More options …

Optical Data Processing and Storage

Editor-in-Chief: Simoni, Francesco

1 Issue per year


Emerging Science

Open Access
Online
ISSN
2084-8862
See all formats and pricing
More options …

Analytical Calculation for Capacitances of Electrode Patterns in Touch Panels

Bau-Jy Liang
  • Corresponding author
  • Dept. of Electrical Engineering, Feng Chia University, Taichung, Taiwan, Province of China40724, R.O.C.,
  • Email
  • Other articles by this author:
  • De Gruyter OnlineGoogle Scholar
/ Don-Gey Liu
  • Dept. of Electronic Engineering, Feng Chia University, Taichung, Taiwan, Province of China 40724, R.O.C.
  • Other articles by this author:
  • De Gruyter OnlineGoogle Scholar
/ Chia-Hung Yeh
  • Dept. of Electrical Engineering, Feng Chia University, Taichung, Taiwan, Province of China 40724, R.O.C.
  • Other articles by this author:
  • De Gruyter OnlineGoogle Scholar
/ Hsiao-Chun Chen
  • Dept. of Electrical Engineering, Feng Chia University, Taichung, Taiwan, Province of China 40724, R.O.C.
  • Other articles by this author:
  • De Gruyter OnlineGoogle Scholar
/ Yu-Chen Fang / Pi-Fang Hung
  • Dept. of Finance, Overseas Chinese University, Taichung, Taiwan, Province of China 40721, R.O.C.
  • Other articles by this author:
  • De Gruyter OnlineGoogle Scholar
Published Online: 2017-07-06 | DOI: https://doi.org/10.1515/odps-2017-0009

Abstract

In this paper, an accurate 3-dimensional (3-D) analytical solution is proposed to calculate the projective capacitances of touch panels. In this study, both simple and complex patterns were investigated for the calculation. We propose a partition strategy to divide a pattern into many rectangular or triangular sub-patterns. Each sub-pattern can be further cut into 2-D slices. The capacitance of a 2-D slice was then solved by our closed-form formulae. The total capacitance of a pattern was obtained by integrating up all the partial capacitances of the slices. In this study, the precision of our analytical method was examined by comparing the simulation results obtained from Q3DTM. The results of our method had a limited deviation from the simulation results while made the computation time from one hour or some by the commercial software down to just a few tens of sec by MatlabTM. In this study, the error is about 5% for simple patterns while the error was within 20% for a very complex pattern.

Keywords: touch panel; capacitor pattern; analytical solution; field-based calculation

References

  • [1] R.N. Aguilar and G.C.M. Meijer, “Fast interface electronics for a resistive touch screen,” in Proc. IEEE Sensors, vol. 2, pp.1360-1363, 2002.CrossrefGoogle Scholar

  • [2] S. P. Hotelling, J. A. Strickon, and B. Q. Huppi, “Multipoint touch screen,” U.S Patent 7, 663, 607, Feb. 16, 2010.Google Scholar

  • [3] S. P. Hotelling and B. R. Land, “Double-sided touch-sensitive panel with shield and drive combined layer,” U.S. Patent 7, 920, 129, Apr. 5, 2011.Google Scholar

  • [4] S. H. Bae, B. C. Yu, S. Lee, H. U. Jang, J. Choi, M. Sohn, I. Ahn, and I. Kang, “Integrating Multi-Touch Function with a Large-Sized LCD,” SID Int’l SymposiumDig. Tech. Papers, pp. 178-181, 2008.CrossrefGoogle Scholar

  • [5] T. J. Knowles, “Touch panel for an acoustic touch position sensor,” U.S Patent 5, 329, 070, Jul. 12, 1994.Google Scholar

  • [6] C. Y. Chang, S. T.Chien, F.Z.Zhang, “Conductor pattern structure of capacitive touch panel,” E.P. Patent 2 650 764, Oct. 16, 2013.Google Scholar

  • [7] Y. K. Hong, H. B. LEE, K. S. CHAE, S. H. Ji, D. S. Yoo, B. C. Lee, S. J. Nam, “Touch panel,” U.S. Patent 0 267 228, Oct. 25, 2012.Google Scholar

  • [8] H. S. Yu, “Sensor for Capacitive Touch Panel Including Mesh Pattern and Capacitive Touch Panel Including the Same,” U.S. Patent 0 299 865, Nov. 29, 2012.Google Scholar

  • [9] R. W. Wang, H. L. Ye, J. Yu, “Touch-control pattern structure, manufacture method thereof and touch panel containing therein,” E.P. Patent 2 527 960, Nov. 28, 2012.Google Scholar

  • [10] P. L. Lo, Y. C. Lin, Y. F. Hsueh, T. M. Chen, “Touch panel,” E.P. Patent 2 639 681 , Sep. 18, 2013.Google Scholar

  • [11] W. H. Ho, Y.C. Chen, Y. C. Lin, “Single-layer and multi-touch projected capacitive apparatus,” U.S. Patent 0 206 379, Aug. 16, 2012.Google Scholar

  • [12] S. F. Wang, K. P. Lee, “Electrode unit with perimeter-lengthened touch-sensing pattern for touch-sensing element located at fringes of touch panel,” U.S. Patent 0 241 851, Sep. 19, 2013.Google Scholar

  • [13] S. J. Kang, K. U. Kim, W. J. Baek, “Electrode pattern for touch screen, driver for touch screen, and touch screen,” U.S. Patent 0 080 353, Apr. 7, 2011.Google Scholar

  • [14] S. F. Wang, “Electrode unit with perimeter-lengthened touchsensing pattern for touch-sensing element located at fringes of touch panel,” U.S. Patent 0 240 342, Sep. 19, 2013.Google Scholar

  • [15] J. Y. Chou, C. Y. Yeh, J. L. Chou, C. K. Lin, C. J. Teng, C. H. Su, “Touch-sensing panel and touch-sensing display apparatus,” U.S. Patent 0 194 213, Aug. 1, 2013.Google Scholar

  • [16] Y. S. Kim, Y. J. Kim, H. Y. Song, H. J. PARK, “Sensing electrode pattern of touch panel,” U.S. Patent 0 162 545, Jun. 27, 2013.Google Scholar

  • [17] K. S. Lee, J. Y. Lee, “Touch screen panel,” U.S. Patent 8 558 805, Oct. 15, 2013.Google Scholar

  • [18] Jeffrey Lee, Matthew T. Cole, Jackson Chi Sun Lai, and Arokia Nathan, "An Analysis of Electrode Patterns in Capacitive Touch Screen Panels," J. Display Technol., vol. 10(5), pp.362-366, 2014.Google Scholar

  • [19] Alan Jeffrey “Advanced Engineering Mathematics,” Academic Press, 2001.Google Scholar

  • [20] S. M. Sharma, S. Dasgupta, and M. V. Kartikeyan, “Successive Conformal Mapping Technique to Extract Inner Fringe Capacitance of Underlap DG-FinFET and Its VariationsWith Geometrical Parameters,” IEEE Tran. Electron. Dev., vol. 64, no. 2, pp. 384-391, 2017.CrossrefGoogle Scholar

  • [21] J. H. Chern, J. Huang, L. Arledge, P.-C. Li, and P. Yang, “Multilevel metal capacitance models for CAD design synthesis systems,” IEEE Electron Device Lett., vol. 13, no. 1, pp. 32-34, Jan. 1992.Google Scholar

  • [22] T. Sakurai, “Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI’s,” IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.Google Scholar

  • [23] U. Choudhury and A. Sangiovanni-Vicentelli, “Automatic generation of analytical models for interconnect capacitances,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 4, pp. 470-480, Apr. 1995.CrossrefGoogle Scholar

  • [24] S.-P. Sim, N. D. Arora, C. Cao, S. Krishan, K. Lee, and C. Y. Yang, “Analytical capacitance model for high-speed interconnects with diagonal routing,” Proc. IEEE Interconnect Tech. Conf., pp. 157-158, 2002.Google Scholar

  • [25] E. A. Dengi and R. A. Rohrer, “Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling,” in Proc. Des. Autom. Conf., pp. 127-132, 1997.Google Scholar

  • [26] Bau-Jy Liang, Don-Gey Liu, Hsiao-Chun Chen, Yu-Chen Fang, Pi-Fang Hung, “A Quick Field-Based Calculation for the Capacitances of Symmetrical Patterns in Touch Panels,” J. Disp. Tech., vol. 12, no. 12, pp. 1629-1637, 2016.Google Scholar

  • [27] Wei Zhao, Xia Li, Sam Gu, Seung H. Kang, Matthew M. Nowak, and Yu Cao, "Field-Based Capacitance Modeling for Sub-65- nm On-Chip Interconnect," IEEE Trans. Electron Dev., vol. 56(9), pp.1862-1872, 2009.Web of ScienceGoogle Scholar

  • [28] W. Zhao , X. Zhu , W. Deng , J. He, A. Chen and M. Chan "Field-based capacitance modeling for sub-65 nm on-chip interconnect", 2012 4th Asia Symposium Quality Electronic Design (ASQED), pp.110 -116 2012.Google Scholar

  • [29] J. Zou, Q. Xu, J. Luo, R.S. Wang, R. Huang, and Y.Y. Wang, “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all- Around Cylindrical Silicon NanowireMOSFETs”, IEEE Trans. Electron Device, vol. 58, no. 10, pp. 3379-3387, Oct. 2011Google Scholar

  • [30] Hsiao-Chun Chen, “Analytical solution on the pattern of projected touch panel,” Master Thesis, Feng Chia University, 2013.Google Scholar

  • [31] Chia-Hung Yeh, “Analytical Solution Improvement on Capacitance Pattern for Projective Capacitance Touch Panel,” Master Thesis, Feng Chia University, 2013.Google Scholar

About the article

Received: 2017-04-17

Revised: 2017-06-05

Accepted: 2017-06-06

Published Online: 2017-07-06

Published in Print: 2017-06-27


Citation Information: Optical Data Processing and Storage, Volume 3, Issue 1, Pages 67–78, ISSN (Online) 2084-8862, DOI: https://doi.org/10.1515/odps-2017-0009.

Export Citation

© 2017. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License. BY-NC-ND 4.0

Comments (0)

Please log in or register to comment.
Log in