[1] S. Asano, T. Maruyama, and Y. Yamaguchi, “Performance comparison of FPGA, GPU, and CPU in image processing”, Proc. I. C. Field Prog. Logic, Prague, 126–131 (2009). Google Scholar
[2] E.J. Kelmelis, F.E. Ortiz, P.F. Curt, M.R. Bodnar, K.E. Spagnoli, A.L. Paolini, and D.K. Price, “Comparing FPGAs and GPUs for high-performance image processing applications”, Proc. SPIE
7701, 77010C–9 (2010). http://dx.doi.org/10.1117/12.850397Google Scholar
[3] K. Mueller, F. Xu, and N. Neophytou, “Why do commodity graphics hardware boards (GPUs) work so well for acceleration of computed tomography?”, Proc. SPIE
6498, 64980N–12 (2007). http://dx.doi.org/10.1117/12.716797Google Scholar
[4] P. Lysaght, “The programmable logic perspective”, http://conferenze.dei.polimi.it/FPL2010/finalprogram.htm Google Scholar
[5] http://www.tridentmicro.com/producttree/tv/dtv/ Google Scholar
[6] K. Wiatr, Hardware Implementation of Image Processing Algorithms in Real-time Video Codecs, AGH University of Science and Technology Press, Cracow, 1998. Google Scholar
[7] T. Komuro, T. Tabata, and M. Ishikawa, “A reconfigurable embedded system for 1000 f/s real time vision”, IEEE T. Circ. Syst. Vid.
20, 496–504 (2010). http://dx.doi.org/10.1109/TCSVT.2009.2035832CrossrefGoogle Scholar
[8] http://www.xilinx.com/products/targeted_design_platforms.htm Google Scholar
[9] http://www.mathworks.com/products/viprocessing/demos.html Google Scholar
[10] http://www.xilinx.com/products/devices.htm Google Scholar
[11] P. Russek, E. Jamro, M. Wielgosz, M. Janiszewski, M. Pietroń, and K. Wiatr, “Computation acceleration on SGI RASC: FPGA based reconfigurable computing hardware”, Comput. Sci.
9, 21–34 (2008). Google Scholar
[12] T. Kryjak and M. Gorgoń, “Pipeline implementation of peer group filtering in FPGA”, Proc. KUKDM 2010: Third ACC Cyfronet AGH Users’ Conf., Zakopane, 27–29 (2010). Google Scholar
[13] A. Gorkic, D. Bracun, and J. Diaci, “Developing a camera with a built in programmable image processor”, Ventil
15, 246–252 (2009). Google Scholar
[14] Ł. Mik and M. Gorgoń, “FPGA-based digital camera with image processing system”, Automatyka
13, edited by AGH University of Science and Technology Press, Cracow, 921–929 (2009). Google Scholar
[15] http://www.nallatech.com/fpga-motherboards.html Google Scholar
[16] R.G. Shoup, “Real time image manipulation using soft hardware”, IEEE Sys. Man Cybern.
3, 343–348 (1993). http://dx.doi.org/10.1109/ICSMC.1993.385035CrossrefGoogle Scholar
[17] M.Z. Zhang, H.T. Ngo, A.R. Livingston, and V.K. Asari, “A high performance architecture for implementation of 2D convolution with quadrant symmetric kernels”, Int. J. Comput. Appl.
30, 298–308 (2008). Google Scholar
[18] S. Rehman, R. Young, C. Chatwin, and P. Birch, “An FPGA based generic framework for high speed sum of absolute difference implementation”, Eur. J. Sci. Res.
1, 6–29 (2009). Google Scholar
[19] J. Chase, B. Nelson, J. Bodily, Z. Wei, and D.J. Lee, “Real-time optical flow calculations on FPGA and GPU architectures: A comparison study”, Proc. 16th Int. Symp. on Field-Programmable Custom Computing Machines, Stanford, 173–182 (2008). Google Scholar
[20] H. Bessalah, F. Alim, M.A. Bencherif, and S. Seddiki, “Toward an embedded image wavelet transform implementation approach”, Transactions on Systems, Signals and Devices
2, 291–310 (2005–2006). Google Scholar
[21] A. Ahmad, B. Krill, A. Amira, and H. Rabah, “Efficient architectures for 3D HWT using dynamic partial reconfiguration”, J. Syst. Architect.
56, 305–316 (2010). http://dx.doi.org/10.1016/j.sysarc.2010.02.001CrossrefGoogle Scholar
[22] D. Han, B. Lee, J.I. Cho, and D.H. Hwang, “Real time object segmentation using disparity map of stereo matching”, Appl. Math. Comput.
205, 770–777 (2008). http://dx.doi.org/10.1016/j.amc.2008.05.110Web of ScienceCrossrefGoogle Scholar
[23] B. Thornberg and N. Lawal, “Real-time component labelling and feature extraction on FPGA”, Proc. IEEE Symp. Signal Circ., Iasi, 4 (2009). Google Scholar
[24] Y. Ito and K. Nakano, “Optimized component labelling algorithm for using in medium sized FPGAs”, Proc. 9th Int. Conf. on Parallel and Distributed Computing, Applications and Technologies, Otago, 171–176 (2008). Google Scholar
[25] L. Yao, H. Feng, Y. Zhu, Z. Jiang, D. Zhao, and W. Feng, “An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher”, I. C. Field Prog. Techn. FPT, Sydney, 30–37 (2009). Google Scholar
[26] S. Saadi, H. Mekki, and A. Guessoum, “Object detection and segmentation algorithm implemented on a reconfigurable embedded platform based FPGA”, T. Signal Process.
4, 552–561 (2008). Google Scholar
[27] H.T. Ngo, R.N. Rakvic, R.P. Broussard, and R.W. Ives, “An FPGA based design of a modular approach for integral images in a real-time face detection system”, Proc. SPIE
7351, 73510B (2009). http://dx.doi.org/10.1117/12.820248Google Scholar
[28] H.C. Nguyen, B.R. Hayes Gill, S.P. Morgan, Y. Zhu, D. Boggett, X. Huang, and M. Potter, “A field programmable gate array based system for high frame rate laser Doppler blood flow imaging”, J. Med. Eng. Technol.
34, 306–315 (2010). http://dx.doi.org/10.3109/03091902.2010.481032CrossrefGoogle Scholar
[29] P. Zhou, Y. Liu, and Y. Wang, “Pipeline architecture and parallel computation based real time stereovision tracking system for surgical navigation”, IEEE. T. Instrum. Mea.
59, 1240–1250 (2010). http://dx.doi.org/10.1109/TIM.2010.2044074CrossrefWeb of ScienceGoogle Scholar
[30] J.J. Koo, A.C. Evans, and W.J. Gross, “3D brain MRI tissue classification on FPGAs”, IEEE. T. Image Process.
18, 2735–2746 (2009). http://dx.doi.org/10.1109/TIP.2009.2028926Web of ScienceCrossrefGoogle Scholar
[31] Z. Voroshazi, Z. Nagy, and P. Szolgay, “FPGA based real time, multichannel emulated digital retina model implementation”, Eurasip. J. Adv. Sig. Pr., art. ID 749838, 10 (2009). Web of ScienceGoogle Scholar
[32] V. Simhadri and Y. Ozturk, “RASCor: An associative hardware algorithm for real time stereo”, Comput. Electr. Eng.
35, 459–477 (2009). http://dx.doi.org/10.1016/j.compeleceng.2008.12.001Web of ScienceCrossrefGoogle Scholar
[33] S. Jin, J. Cho, X.D. Pham, K.M. Lee, S.K. Park, M. Kim, and J.W. Jeon, “FPGA design and implementation of a real time stereo vision system”, IEEE T. Circ. Syst. Vid.
20, 15–26 (2010). http://dx.doi.org/10.1109/TCSVT.2009.2026831CrossrefGoogle Scholar
[34] X.Y. Hong, Z.Y. Fang, D. Xin, and L.J. Lin, FPGA implementation of non-parametric stereo matching algorithm”, J. Zhejiang Univ.
43, 250–254 (2009). Google Scholar
[35] M. Moradi, M.A. Poormina, and F. Razzazi, “FPGA implementation of feature extraction and LP neural network classifier for Farsi handwritten digit recognition”, Proc. 3d UK Sim Eur. Symp. on Computer Modelling and Simulation, 231–242, 2009. Google Scholar
[36] J. Konieczny and A. Luczak, “A scalable motion estimation algorithm for distributed systems”, PAK
55, 684–686 (2009). Google Scholar
[37] K.S. Park, S.H. Cho, S. Hong, and W.D. Cho, “Real-time target detection architecture based on reduced complexity hyperspectral processing”, Eurasip. J. Ad. Sig. Pr., art. 438051 (2008). Google Scholar
[38] M. Gorgoń, “Reconfigurable architectures for parallel execution of image processing tasks”, Opto-Electron. Rev.
15, 196–201 (2007). http://dx.doi.org/10.2478/s11772-007-0019-3Web of ScienceCrossrefGoogle Scholar
[39] M. Jabłoński, “On paralellization of machine vision algorithms in data-stream-driven system”, PhD Dissertation, AGH-UST, Cracow, 2009. (in Polish) Google Scholar
[40] J.L. Gustafson, “Reevaluating Amdahl’s law”, Commun. ACM
31, 532–533 (1988). http://dx.doi.org/10.1145/42411.42415CrossrefGoogle Scholar
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