Transmission electron microscopy methods were used to determine the impact of two different implantation processes on the morphology of platinum silicide layers constituting low Schottky barrier contacts intended as the source/drain in MOS transistors. These processes are very promising candidates for the reduction of the Schottky barrier height (SBH) of contacts and are realized by (i) implantation-through-metal (ITM) followed by dopant-segregation induced by silicidation annealing and (ii) implantation-through-silicide (ITS) followed by dopant-segregation due to the post-silicidation annealing. The studies showed that depending on the type and conditions of the process (ITM or ITS with various post-silicidation annealing temperatures) different morphologies of PtSi layers and PtSi/Si interfaces roughnesses are observed. Better quality silicide layers and silicide/silicon interfaces were found for samples after the ITS process with post-silicidation annealing at 500°C than for samples after the ITM process or the ITS process with post-silicidation annealing at temperatures not exceeding 400°C.
The observed microstructure of grains and interfaces in these samples, along with the impact of the dopant-segregation, may significantly influence the SBH value. The diffraction patterns and EDXS measurements revealed that regardless of the process type, the formed silicide layer is always PtSi.