PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

K. Rahimunnisa 1 , P. Karthigaikumar 2 , N. Christy 1 , S. Kumar 3  and J. Jayakumar 4
  • 1 Department of Electronics and Communication Engineering, Karunya University, Coimbatore, 641 114, India
  • 2 Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, 641 032, India
  • 3 Department of Electrical and Electronics Engineering, Dr. NGP Inst. of Technology, Coimbatore, 641 048, India
  • 4 Department of Electrical and Electronics Engineering, Karunya University, Coimbatore, 641 114, India


As the technology is growing day by day, information security plays a very important role in our lives. In order to protect the information, several cryptographic algorithms have been proposed. The aim of this paper is to present an effective Advanced Encryption Standard (AES) architecture to achieve high throughput for security applications. The Parallel Sub-Pipelined architecture (PSP) is proposed in order to obtain high throughput. The proposed architecture is also compared with loop unrolled, pipelined, sub-pipelined, parallel and parallel pipelined architecture in terms of throughput. The AES algorithm using Parallel Sub-Pipelined architecture was prototyped in FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit).The proposed architecture yielded a throughput of 59.59 Gbps at a frequency of 450.045 MHz on FPGA Virtex XC6VLX75T which is higher than the throughput yielded in other architectures. In ASIC 0.13 µm technology, the proposed architecture yielded a throughput of 25.60 Gbps and in 0.18 µm, it yielded a throughput of 20.56 Gbps.

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  • [1] National Inst. of Standards and Technology (NIST), Federal Information Processing Standard Publication 197, the Advanced Encryption Standard (AES), 2001

  • [2] P. Karthigaikumar, K. Baskaran, An ASIC implementation of low power and high throughput blowfish crypto algorithm, Microelectr. J. 41, 347–355, 2010

  • [3] L. Liu, D. Luke, Implementation of AES as a CMOS core, IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Canada, May 5–8, 2013

  • [4] A. Kaminsky, M. Kurdziel, S. Radziszowski, An Overview of Cryptanalysis Research for the Advanced Encryption Standard, Military Communication Conference, CA, Oct 31–Nov 3, 2010

  • [5] N. Courtois, J. Pieprzyk, Cryptanalysis of Block Ciphers with Overdefined Systems of Equations, ASIACRYPT, LNCS, Queenstown, Dec 1–5, 2002

  • [6] N. Courtois, A. Klimov, J. Patarin, A. Shamir, Efficient Algorithms for Solving Overdefined Systems of Multivariate Polynomial Equations, EUROCRYPT, LNCS, Kyoto, Dec 3–7, 2000

  • [7] A. Kipnis, A. Shamir, Cryptanalysis of the HFE Public Key Cryptosystem by Relinearization, CRYPTO, LNCS, California, Aug 15–19, 1999

  • [8] A. Biryukov, O. Dunkelman, N. Keller, D. Khovratovich, A. Shamir, Key Recovery Attacks of Practical Complexity on AES Variants with up to 10 Rounds, EUROCRYPT, French Riviera, May 30–June 3, 2010 (Springer, 2010)

  • [9] S. Mangard, M. Aigner, S. Dominikus, A Highly Regular And Scalable AES Hardware Architecture, IEEE T. Comp. 52(4), 483–491, 2003

  • [10] O. Harrison, J. Waldron, AES Encryption Implementation and Analysis on Commodity Graphics Processing Units, 9th Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), Vienna, Sept 10–13, 2007

  • [11] H. Li, Z. Friggstad, An EfïnAcient Architecture for the AES Mix Columns Operation, IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23–26, 2005

  • [12] G. Rouvroy, F.-X. Standaert, J.-J. Quisquater, J.-D. Legat, Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications, International Conference on Information Technology: Coding and Computing, Las Vegas, April 5–7, 2004

  • [13] C. J. Chang, C. W. Hu, K. H. Chang, Y. C. Cheng Chen, C. C. Hsieh, High Throughput 32-bit AES Implementation in FPGA, IEEE Asia Pacific Conference on Circuits And Systems (APCCAS), Macao, Nov 30–Dec 3, 2008

  • [14] C. P. Fan, J. K. Hwang, FPGA implementations of high throughput sequential and fully pipelined AES algorithm, Int. J. Elec. Eng. 15(6), 447–455, 2008

  • [15] I. Hammad, K. El-Sankary, E. El-Masry, High Speed AES Encryptor with Efficient Merging Techniques, IEEE Embedded Syst. Lett. 2(3), 67–71, 2010

  • [16] A. Hodjat, I. Verbauwhede, A 21.54 Gbits/s Fully pipelined AES Processor on FPGA, Proc. of the 12th annual IEEE Symposium on Field Programmable Custom Computing Machines (FCCM’04), Boston, May 11–13, 2004

  • [17] A. Hodjat, I. Verbauwhede, Area Throughput Trade Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors, IEEE T. Comput. 55(4), 366–372, 2006

  • [18] S. K. Reddy, R. Sakthivel, P. Praneeth, VLSI Implementation of AES Crypto Processor for High Throughput, Int. J. Adv. Eng. Sci, Tech. 6(1), 22–26, 2011

  • [19] E. J. Swankoski, R. R. Brooks, V. Narayanan, M. Kandemir, M. J. Irwin, A Parallel Architecture for Secure FPGA Symmetric Encryption, Proceedings in 18th International Symposium on Parallel and Distributed Processing Symposium, New Mexico, April 26–30, 2004

  • [20] X. Zhang, K. K. Parhi, High speed VLSI Architectures for the AES Algorithm, IEEE T. VLSI. Syst. 12(9), 957–967, 2004

  • [21] M. Fayed, W. M. El-Kharashi, F. Gebali, A high speed, Fully Pipelined VLSI Architecture for real time AES, 4th International Conference on Information and Communications Technology (ICICT), Egypt, Dec 1–2, 2006

  • [22] H. Li, J. Li, A high performance sub-pipelined architecture for AES, IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), Cambridge, October, 2005

  • [23] L. Henzen, W. Fichtner, FPGA Parallel-Pipelined AES-GCM core for 100G Ethernet applications, Proceedings of ESSCIRC, Seville, September 13–17, 2010

  • [24] S.-S. Wang, W.-S. Ni, An Efficient FPGA Implementation of Advanced Encryption Standard Algorithm, Proceedings of International Symposium on Circuits and Systems, Vancouver, May 23–26, 2004

  • [25] M. K. Sirin, D. K. Mahesh, D. Y. Rama, High Throughput-Less Area Efficient FPGA Implementation of Block Cipher AES Algorithm, International Conference on Advanced Computing, Communication and Networks, Chandigarh, June 2–3, 2011

  • [26] H. Qin, T. Sasao, Y. Iguchi, An FPGA Design of AES Encryption Circuit with 128-bit Keys, Proceedings of the 15th ACM Great Lakes Symposium on VLSI (GLSVLSI), Illinois, April 17–19, 2005

  • [27] J. M. Granado Criado, M. A. Vega Rodriguez, J. M. Sanchez Perez, J. A. Gomez Pulido, A new methodology to implement the AES algorithm using partial and dynamic reconfiguration, Integration 43, 72–80, 2010

  • [28] K. Thongkhome, C. Thanavijitpun, S. Choomchuay, A FPGA Design of AES core architecture for portable hard disk, 8th International Conference on Computer Science and Software Engineering (ICSSE), Thailand, May 11–13, 2011

  • [29] Y. Zhang, X. Wang, Pipelined Implementation of AES Encryption based on FPGA, IEEE Conference on Information Theory and Information Security (ICITIS), Beijing, Dec 17–19, 2010

  • [30] N. C. Iyer, P. V. Anandmohan, D. V. Poornaiah, V. D. Kulkarni, High throughput, low cost, fully pipelined architecture for AES crypto chip, India Conference, Annual IEEE, India, Sept 15–17, 2006

  • [31] S. M. Yoo, D. Kotturi, D. W. Pan, J. Blizzard, An AES crypto chip using a high speed parallel pipelined architecture, Microproc. Microsy. 29, 317–326, 2005

  • [32] T. Good, M. Benaissa, 692-nW Advanced Encryption Standard (AES) on a 0.13-µm CMOS, IEEE transactions VLSI Syst. 18(12), 1753–1757, 2010

  • [33] S. S. Naqvi, S. R. Naqvi, S. A. Khan, S. A. Malik, Application Specific Scalable Architectures for Advanced Encryption Standard (AES) Algorithm, WSEAS T. Elec. 10(5), 427–436, 2008

  • [34] A. W. Luo, Q. M. Yi, M. Shi, Design and Implementation of Area-optimized AES based on FPGA, International Conference on Business Management and Electronic Information (BMEI), Guangzhou, May 13–15, 2011

  • [35] A. Alma’aitah, Z.-E. Abid, Area Efficient High Throughput Sub-Pipelined Design of the AES in CMOS 180nm, 5th International conference on Design and Test Workshop (IDT), Abu Dhabi, Dec 14–15, 2010

  • [36] Y. Liang, Y. Li, C. Zhang, High Throughput Cost-Effective and Low Power AES Chip Design, 3rd International Congress on Image and Signal Processing, China, Oct 16–18, 2010

  • [37] H. S. Choi, H. Ch. Joong, J. T. Kim, Low Power AES Design using Parallel Architecture, International Conference on Convergence and Hybrid Information Technology, Korea, Aug 28–30, 2008

  • [38] S. Qu, G. Shou, Y. Hu, Z. Guo, Z. Qian, High Throughput, Pipelined Implementation of AES on FPGA, International Symposium on Information Engineering and Electronic Commerce, Ternopil, Ukraine, May 16–17, 2009

  • [39] P. Hamalainen, T. Alho, M. Hannikainen, T. D. Hamalainen, Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core, 9th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD’06), Croatia, Aug 30–Nov 1, 2006


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