This paper presents an integrated and coordinated cross-layer sensing and optimization flow for distributed dark silicon
management for tiled heterogeneous manycores under a critical temperature constraint. We target some of the key challenges
in dark silicon for manycores, such as: directly focusing on power density/temperature instead of considering simple
per-chip power constraints, considering tiled heterogeneous architectures with different types of cores and accelerators,
handling the large volumes of raw sensor information, and maintaining scalability. Our solution is separated into three
abstraction layers: a sensing layer (involving hardware monitors and pre-processing), a dark silicon layer (that derives
thermally-safe mappings and voltage/frequency settings), and an agent layer (used for selecting the parallelism of
applications and thread-to-core mapping based on alternatives/constraints from the dark silicon layer).
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